AMD's Q2 07 Earnings

Looking at the earnings, I'm reminded of the movie "Regarding Henry" where Henry gets shot in the head and is in a coma. The doctor then tells Henry's wife that if you have to get shot in the head that the place where Henry got hit is the best place. Similarly with AMD, I suppose that they had to lose $600 Million in one quarter that this was the best way to do it. Athough the amount of the loss this quarter was the same as last quarter, in other important ways, this quarter was a bit better.

Since there is not much good to say about losing over half a Billion dollars for the third quarter in a row, let's leave that for the moment and look at microprocessor revenue share. AMD's microprocessor revenue share really tanked in Q3 2002 when it hit a low of 5.5%. However, this number is not really comparable to today since at that time AMD had only one FAB capable of producing microprocessors, so AMD didn't need as much of the market. With two FABs today, AMD's costs are higher and therefore AMD needs more share. To compare today's numbers we need to look at the period since AMD started putting serious resources into a second leading edge FAB. Ground breaking on FAB 36 started November, 2003 so we will only compare the current quarter with AMD's history back to Q1 2004.

AMD's microprocessor revenue share climbed from around 9% in early 2004 to about 15% in Q3 2005. AMD's revenue share stayed above this until it fell drastically in Q1 2007 when it hit 13.3%. However, this quarter it bounced up to 15.8% which just a little higher than AMD had in Q4 2005. AMD's processor unit volume has probably also recovered to about what it was before Q1 which would be about 25%. In trying to evaluate these numbers most people stumble over the concept of Average Selling Price or ASP. While it might seem immediately intuitive that higher income is related to higher ASP this is not actually the case. The number we actually need is Average Selling Profit. For example, it would be better to sell a processor for $50 that costs us $20 to manufacturer than to sell a processor for $100 that costs us $80 to make. Unfortunately, average profit for processors is never mentioned. Logically, the number of units sold x average profit = total profit. It means very little to us if AMD's average price increases because this merely increases the total revenue but may not in fact increase profits. However, the numbers show that the cost of producing microprocessors at AMD has dropped by 8.5%. This boosts the profit by 18%. This is seen in the increase of gross margin percent from 28.1% last quarter to 33.5% this quarter. So, AMD's actual average asking price may be lower this quarter than last but it doesn't matter because on average AMD is making more money off of each processor than it did last quarter. Increased unit volume and better profit per unit are both positive changes for AMD this quarter.

I had estimated previously that AMD could lose another $1.5 Billion this year without danger of bankruptcy. Having just lost $600 Million this margin is now down to $900 Million. AMD was also in danger of having its R&D and capital purchases budget choked by its reduced income. For example, AMD had originally planned to spend $2 Billion in 2007 for capital purchases but then had to reduce this estimate to $1.5 Billion. Recently though, the German government pledged $360 Million in aid and AMD's capital purchases estimate climbed again to $1.8 Billion. Also, AMD believes that it can break even in Q4. If this is realistic and Q3 splits the difference losing $300 Million then AMD would pull out of its nosedive with $600 Million to spare. However, trying to estimate Q3 revenue is not easy. AMD's recent price cuts will affect Q3. However, as AMD now takes down FAB 30 they will get increasing benefits of a greater 65nm to 90nm mix. AMD could also see income of $100 - $200 Million in Q3 from sales of 200mm tooling from FAB 30. And, AMD gets at least some benefit from K10 Opteron sales in Q3. To me, this seems like enough to cut the losses by $100 Million or so but not $300 Million unless AMD sees increases in unit volume. This could happen perhaps if DTX is more popular than current solutions. Q4 looks much better. The volume of K10 server chips should be reasonable in Q4 and AMD should begin delivering HT 3.0 capable Budapest versions. Assuming that AMD can bump the clocks up from a paltry 2.0Ghz to a more reasonable 2.3 - 2.5Ghz AMD should gain a little on Intel. On Intel's part, the decision to push back 45nm production at the Chandler FAB to Q1 2008 means that only D1D will be producing 45nm chips in Q4 2007. This volume wouldn't go very far on the desktop but would have some effect on servers. Assuming Intel's 45nm server chips are available in 3.2Ghz speeds, AMD will need at least 2.4Ghz quad cores.

To some extent this is like walking up a down escalator. AMD will certainly increase clock speeds in Q4 but it appears that Intel will as well. Essentially, AMD will use its K10 chips to maximum benefit as Opterons because Current Opterons are still running on the old 90nm process. So, Opteron gets higher IPC, greatly enhanced power saving features, and power savings due to 65nm. AMD's greatest advantage will be in 2-way or 4-way where Intel's use of FBDIMM makes Intel systems consume more power and run slower. However, Intel too gets power savings from 45nm and its larger cache will help the most on 2-way and up quad core systems. So, AMD's advances will get mostly countered by similar advances from Intel. AMD will come out only slightly ahead in power/watt on 2-way and up systems due to faster HT, enhanced power saving, and inherent advantages of native versus MCM quad. On the other hand, Intel retains highest overall performance due to its much greater clock speed. In Q1 2008 the race continues as Intel ramps 45nm desktop chips while AMD ramps K10 desktop chips. Then in Q2 Intel ramps 45nm mobile while AMD delivers its most aggressive mobile offering with a new mobile cpu and all new mobile chipset. The situation continues in the second half of 2008 as Intel gears up for Nehalem with Integrated Memory Controller and CSI (similar to AMD's HyperTransport) while AMD gears up for its own 45nm chips with Direct Connect Architecture 2.0 (including a possible MCM octal core). Production in 2008 should be similar as Intel ramps two new 45nm FABs while AMD converts 200mm FAB 30 to 300mm FAB 38 and finally enjoys the benefits of having two similar 300mm FABs.

I suppose I'm somewhat reminded of the mythical hydra when thinking of Intel's current FSB based chipset solutions. With each head that was cut off, the hydra would grow two more. In a similar fashion Intel has attempted to overcome the problems of shared bus by having first two FSB's and then four FSB's later this year. I've seen some people naively describe this as two of Intel's current 5000 series northbridge chips. However, quad FSB chipset complexity is not twice that of a dual FSB chipset, but actually four times greater if the same speed is maintained or half the speed with similar complexity. If we simply linked two northbridges together we would incur a large latency penalty between the northbridges every time we transferred from memory across chips. So, we put all the functions in one chip. This sounds great but look at the numbers. For two FSB's and two FBDIMM channels we have 2x4 = 8 connections. To maintain the same bandwidth for four FSB's we would need eight FBDIMM channels for 4x8 = 32 connections. Four times the connections means four times the circuitry and four times the power draw. This is a reasonable interim solution for Intel but we can also understand why Intel will drop this architecture with Nehalem.

Some have tried to compare the release of K10 to K8 in 2003. I assume this analogy comes to mind because of AMD's less competitive position with K7 and because of both K8's delays and low initial clock speeds. However, they are actually quite different. The K8 die was twice the size of the K7 die and yields on the new 130nm SOI process were terrible at about half of K7's yields. Also, the only available chipset at K8's release was AMD's own 8000 series. It took months for desktop motherboards to begin showing up. In contrast, K10's 65nm yields are good and it already has full support with existing AM2 and socket F motherboards. Another similarity is that in 2003, Xeon's FSB was woefully underpowered on 4-way systems which is why Xeon relied heavily on L3 cache. Clearly, Intel is still relying on large cache as shown by Yorkfield's 50% increase but Intel today is much more competitive in FSB speed. In 2003, 4-way Xeon used DDR-266 compared to Opteron's DDR-400. Today, AMD's memory controller is equivalent to a FSB speed of 1600 Mhz. The same ratio as 2003 would put Intel at 1066 Mhz so we can see that Intel is already ahead of this at 1333 Mhz. Further, since AMD already uses the fastest DDR2-800 memory, greater controller speeds won't help unless DDR2-1066 is released. In fact, if DDR2-1066 is not released, AMD's lead in memory speed is likely to vanish as AMD won't switch to DDR3 until late 2008. This is essentially what happened with DDR where Intel influenced JEDEC to stop at DDR-400 and switch to DDR2 while AMD could have used DDR-500. It is possible that after the lackluster acceptance of Intel's FBDIMM that JEDEC might be more open. However, it remains to be seen if JEDEC will continue to follow Intel or whether they will be more supportive of AMD.

The final thing that I've been curious about is the change in processors families. When AMD had K7, all of their market segments were covered with this one architecture. So, AMD had the dual socket MP version of K7, the mobile version of K7, and the low end Duron version. AMD continued this same approach with K8 with Opteron, Turion, and Sempron. Intel in contrast has often had very different architectures for different segments. For example, Intel continued to sell Pentium Pro for servers even after PII was launched. Further, Intel's Celeron version with on-die cache instead of off-die cache was also quite different in architecture. Intel continued this with P4 Xeon by using L3 cache and PAE addressing which was not used in the desktop version. We see the same thing today where Tulsa with its hybrid FSB design is also substantially modified from the desktop version. Intel changed this even further with Pentium M whose architecture was very different from P4's. Today though Intel has reversed this situation by using one architecture for everything. Intel has Conroe, Woodcrest, and Merom versions of C2D much as AMD had with K8. Apparently Intel will continue this with 45nm by having Wolfdale, Yorkfield, and Penryn versions. AMD however is going the other way and will release a new mobile architecture called Puma in 2008 based not on K10 but a development of K8. The main difference that I can see is that Puma is not designed around massive throughput SSE as the desktop and server chips are. This may be a reasonable architecture split since I suspect few people do video or audio bulk conversion or other SSE intensive tasks on their notebooks. If this really is an advantage then it is certainly possible that Intel will go back to a split architecture when it introduces Nehalem. In fact there have already been suggestions that only the multi-socket versions will use an IMC while Intel will continue to use a FSB with the single socket chips. If true this would indeed put Intel back into a split architecture strategy.