What Quads May Come

I had a technical look at AMD's K8L in AMD Unveils Barcelona Quad-Core Details . There are improvements that I had not heard about before. There are several that should make a difference and boost both K8L's SSE and Integer performance. From this information it appears that 2007 will be much tougher for Intel and that it will lose most if not all of the ground it gained with the release of Core 2 Duo.

The K8L architecture seems to have more tweaks than I had first thought. There are many changes that pull AMD up to where Intel is now with Core 2 Duo. For example, Intel has had a dedicated stack unit since Pentium M and now AMD matches this with its own Sideband Stack Optimizer. Intel has been ahead of in out of order execution and AMD moves closer with enhanced reordering and some out of order loading. Intel had already increased the size of the reorder buffer.

AMD now has data dependent latency on the divide instruction as Intel had already done. AMD greatly improves SSE width and the number of SSE operations. It doubles the bandwidth of Prefetch and the L1 bus. Again, these are changes that Intel had made from Yonah (Core Duo) to C2D. AMD might have a small advantage here due to twin L1 buses rather than just a wider L1 bus.

It is also no secret that AMD's K8 architecture works better with lower latency memory like DDR. Intel has been pushing Jedec toward DDR2 and higher because its larger cache tends to reduce the bad effects of latency while it hurts AMD's smaller cache architecure more. However, AMD is now moving to a split memory controller where each half can act independently. This along with the larger L3 cache, improved memory scheduling, a better write burst mode, and out of order loads more than makes up for the higher latency of DDR2. We should see a big improvement for AMD with DDR2 and into DDR3. This again, moves AMD up to where Intel is now.

AMD's L3 is also more complex than I had thought. I had expected the L3 to be exclusive but AMD has apparently decided to make it more complex. They use it exclusively with data but can use it inclusively with instructions. This is a big improvement and would tend to negate most of Intel's advantage with inclusive cache and its advantage with the shared L2. However, this multi-mode function allows AMD to retain its current cache size flexibility. It would be able to change the size of both L2 and L3 without a severe penalty in performance. Intel does not have this flexibility. Further, Intel's use of shared L2 leaves the processor vulnerable to cache thrashing where one thread pushes instructions out of the L2 only to have its own instructions pushed out by the first thread in a cpu clock wasting tug of war.

AMD is expanding the number of FastPath instructions. This is important because the decoders can do 3 fastpath instructions or 1 complex instruction. The more instructions that are fastpath the better. This again makes up for some of the improvement that Intel gained by adding a fourth decoder and macro-ops fusion. This is also helped by doubling the Prefetch as Intel has done.

Overall, AMD moves much closer to Intel's C2D with the changes in K8L. AMD will add to its already greater memory access speed and match or beat C2D in terms of SSE. However, the changes don't quite add up to C2D's 4 instruction issue and Macro-ops fusion. I would guess that AMD will remove about 3/4 of the current IPC gap. This would mean that a K8L of 3.1 Ghz would match a C2D of 3.0 Ghz. This is much better than today where it would take a 3.5 Ghz K8 to match the same 3.0 Ghz C2D.

I am very curious to see how the testing will go when K8L is released as Antares for the desktop in Q3 07. There are so many improvements that move K8L closer to C2D that it will be difficult to bias the testing in Intel's favor. I'm guessing that when Intel is faced with the threat of K8L and the imminent loss of its performance advantages it will be sure to rush the new 45nm chips into reviewer's hands. Even these new chips though will probably not be enough to regain the C2D lead. I'm guessing that review sites like Tom's Hardware Guide and Anandtech will fall back on the classic cheat of comparing an overclocked Intel chip against a stock AMD chip. I can always hope that if the loss of Intel's lead becomes unavoidable that perhaps THG and Anandtech will even do some real testing with the second core (or other three cores on quads) loaded properly. They might even do some testing that actually stresses the memory bandwidth. I think that right now with the C2D lead that it is just too tempting for them to push the tests in Intel's favor and avoid real testing that would make C2D more even like loaded testing. It is generally expected that C2D will bog down under load more than K8. I'm still wondering how the review sites will avoid testing Barcelona (K8L Opteron quad) against Clovertown since Clovertown is expected to fair pretty badly in such a test. I guess we will see.