Tigerton or Kittenton? Memory Amnesia.

The glowing reports about Intel's roadmap for 2007 continue. Central in this enthusiasm is the native quad core Tigerton which is supposed to be the platform that will keep Intel ahead of AMD's K8L technology. However, in evaluating this platform most people seem to have forgotton the memory bandwidth lessons from P4 and Athlon 64. This amnesia of memory requirements has led to exagerated expectations of performance for Tigerton.



The diagram above for Tigerton looks impressive. Surely four buses with an aggregate bandwith of 34 GB/sec would be enough. Or would it? Just think back to 2002 and 2003 when P4 was so strong against K7. I remember how Intel enthusiasts bragged about the 800Mhz FSB for P4 which was well ahead of what K7 had. Curiously, while these same Intel enthusiasts thought 800Mhz was necesary for one core they now seem to be insisting that 1066Mhz is enough for four cores. Let's consider this more carefully.

We know that when Intel increased its FSB from 400Mhz to 800Mhz that it didn't use all of the bandwidth. We also know that Athlon 64 seemed to get along okay on socket 754 which only contained one memory channel. One memory channel on socket 754 was basically the same as the 400Mhz FSB for P4. It is difficult to imagine that anyone today would suggest that this was more bandwidth than these processors needed. I think clearly that this level for one core is the most reasonable starting point. Let's see where this takes us.

If we need one memory channel with DDR 400 for one Athon 64 core then the dual memory channels with socket 939 and 940 would seem to be enough for X2. Likewise, an 800Mhz FSB with two channels of DDR 400 or DDR2 400 should be enough for Intel's dual core Preslers, Conroes, and Woodcrests. If this is the standard then both AMD and Intel clearly have more bandwidth than necessary for dual cores. AMD's Integrated Memory Controller (IMC) allows expansion beyond two sockets and Intel's 5000 series chipset with two buses again allows expansion to two sockets with similar memory bandwidth. Dual core today is well in hand. Let's look at more cores.

Intel will soon release the quad core Kentsfield and AMD will release the quad core Barcelona in Q2 07. The above diagram is for Tigerton which most likely would arrive in Q4 07 but could arrive in Q3 07. Although Intel does say Q3 07 the chips may not arrive in volume for another two months if recent releases are any indication. At any rate, we know that dual core works well but will quad core work the same? If an 800Mhz FSB is required for dual core then reasonably a 1600Mhz FSB would be needed for Kentsfield or Tigerton. We know that Kentsfield will have a 1333Mhz FSB at most and may only have 1066Mhz. A FSB of 1333Mhz would only be equivalent to a Conroe with a 667Mhz FSB. This would be equivalent to a 333Mhz FSB for P4. We can probably skip comparing with a 333Mhz FSB single core P4 because it is possible that the longer pipeline changed the bandwidth requirements. Since Core 2 Duo (C2D) is not available in single core it seems reasonable to compare with the single cored Athlon 64 which also has shorter pipeline. For Athlon 64 this would be the same as using the single channel socket 754 and using DDR 333.

It does seem curious that no one uses a Conroe with the FSB set at 667Mhz since this is what is being claimed is adequate for Kentsfield. However, the question of whether or not Kentsfield can do 1333Mhz on its FSB is moot since the above diagram for Tigeron only shows an aggregate of 34 GB/sec for four buses. 34 GB/sec for four buses is only 1066Mhz per bus. This is only equivalent to a Conroe with a 533Mhz FSB or a P4 with a 266Mhz FSB. The equivalent for AMD would be an X2 or Athlon 64 with DDR 266 on socket 754. To make things worse, the memory speed listed in the diagram is incorrect. To keep up with four FSB's running at 1066Mhz, Intel will need DDR2 (or DDR3) running at 1066Mhz as well. The only way that the above diagram would work with 667 Mhz memory would be if the number of memory buses is wrong and it actually has six memory buses instead. However, even if the memory is able to keep up the FSB speed is inadequate for four sockets.

As far as I can tell the only reason for this recent outbreak of amnesia for memory requirements is the sloppy testing over at Tom's Hardware Guide. Apparently, THG is on some kind of crusade to prove that Intel has the best hardware even if THG has to fake the tests to prove it. It doesn't seem to do any good to criticize the testing at THG because the excuses from Intel enthusiasts seem to grow exponentially in proportion to how bad the testing is. However, not matter how sloppy or unprofessional or biased the testing is at THG there really is no escaping common sense. A Tigerton with four buses of 34 GB/sec aggregate bandwidth is only equivalent to a Conroe with a 533Mhz FSB. I'm curious why THG doesn't run a Woodcrest test with the FSB set to 533Mhz to show what the expected performance with Tigerton will be. Tigerton should be double a Woodcrest with 533Mhz FSB. The comparative proof for Kentsfield is easy as well since you only need to set the FSB to half the FSB speed for Kentsfield to get the same memory bandwidth.

The notion that a Tigerton can run four cores with a FSB of 1066Mhz is beyond ridiculous. This would only be 533Mhz for Conroe and equivalent to DDR 266 for both X2 and Athlon 64 on socket 754. Even the old Barton Athlon XP 3200+ used a FSB of 400. To get as low as Tigerton we would have to go all the way back to the Athlon 2600+ which used a 266Mhz FSB. None of the P4's were ever this low as even the original 1.4Ghz Williamette's had 400Mhz FSB's. We would have to go back to the PIII to get down to 266Mhz on the FSB.

It is clear that memory bandwidth is going to be a serious problem for Intel and is going to set Tigerton's performance back badly. The question then is how well AMD stacks up in the memory bandwidth race. The socket 753 Athlon 64 used one channel of DDR400 memory. This was doubled to two channels with socket 939 and 940 so this would be the same equivalent bandwidth for X2. Presumably, Barcelona would need double this or 800Mhz memory. This shouldn't be a problem as even the memory controller on Revision F is about to handle DDR2 800. This would be equivalent to 1600Mhz and well ahead of the 1066Mhz for Tigerton. In fact, a little math shows that this is fully 50% more bandwith than Tigerton will have. This means that in memory intensive operations Tigerton will bog down to 33% slower than Barcelona or you could also say that Barcelona will be 50% faster.

Looking at the Caneland chipset I can say that moving to quad buses is a step up from the limited dual bus 5000 chipset. I can also say that the 64 MB snoop filter cache is a great idea. This is basically a map that prevents cache coherency traffic from being retransmitted across to other buses unnecessarily. However, this is bad because it indicates that the FSB will still carry the cache coherency messages. The snoop filter won't help when the cache coherency messages must be transmitted to another bus. It is not nearly as good as AMD's design where none of the cache coherency messages effect memory bandwidth. It is also disappointing to see that Intel will still be using the outdated MESI protocol rather than a more advanced protocol like MOESI as AMD uses. This too would reduce cache coherency saves and loads. When another chip needs to access a memory location that is in another chip's cache, MESI requires that chip that has the data save it to memory whereas MOESI can allow sharing without having to save.

The Tigerton server chip is an upgrade to Woodcrest and will at least give Intel something to replace its aging Cedar Mill Xeon chips and finally let C2D go beyond 2-way. However, because of memory bandwidth constraints, Tigerton will be proportionately slower than Woodcrest. Secondly, the octopus-like design of the Caneland Northbridge with four FSB's and four memory buses is not going to be compact or inexpensive. Finally, this limited four bus design will not allow Tigerton to move up to bigger 8-way and 16-way server designs as AMD will have. In conclusion, it appears that although Tigerton looks good, it will be held back by the memory bandwidth of the Caneland platform which is as low as what was used by PIII and Athlon 2600+. This will cause Tigerton to get beaten badly in memory intensive applications, making it more of a kitten than a tiger. Clearly, memory bandwidth will be Intel's biggest problem into 2009.