Sunday, May 27, 2007

AMD's Outlook

I showed in my last article that bankruptcy for AMD is unlikely in 2007. I also showed that benchmark code should use the PGI compiler since it is faster for Intel as well. But, let's concentrate just on where AMD is and where it needs to be.

AMD's luck has not been good lately. They've seen a sharp drop in revenue in Q1 that will probably be matched in Q2 and that will almost certainly make three quarters in a row with an average loss of $500 Million (for $1.5 Billion total). And, whereas AMD had good success with Nexgen, DEC, and IBM the ATI merger seems a bit different. While it isn't a total failure like AMD's later collaboration with Motorola and UMC, it does seem more of a work in progress. It also appears that AMD is going to have to have another revision of Barcelona before launch.

For discreet graphics, R600 is not exactly a success. The delay to May is now followed more delays and less than stellar performance for the 1900. Fuad has suggested that not only is AMD going to move to the 65nm process with R650 but that ATI is going to make some tweaks to the architecture as well. Basically, this means three things. It means that R650 is going to solve the current 1900 heating and power problems. It also means that R650 is much more than a simple shrink of R600. However, this means that R650 is what R600 should be right now so ATI has to be seen as trailing by about half a generation. R650 should be able to finally move beyond the current barrier of 8800GTS performance and get up to 8800GTX where it needs to be. Obviously, nVidia is going to tweak its own designs so there will be something faster by then however there is no doubt that R650 will close up some of the current large gap in performance. Beyond this it remains to be seen if AMD will still be trailing when R700 is released or whether these delays will delay it as well. This does indeed bring into question whether the ATI merger is helping or hurting ATI. My guess is that these problems were all in place at ATI before AMD even considered the merger and I would say that AMD is currently scrambling to give ATI some very needed assistance. AMD does seem to know where the problems are so its a question of how quickly they can get them fixed.

Barcelona now appears to be delayed further into Q3. Most likely, another revision was needed to fix some remaining bugs. Another revision means at least a two month delay and this seems to match with the latest release statements. The INQ suggested that the current revision was ready to go but it looks to me like they got it wrong. I'm also inclined to believe another revision was needed because it looks like AMD is trying to compress the transition from Opteron server chips to Phenom desktop chips to be able to hit the December buying season. AMD will also have to do this in the face of another round of price cuts from Intel, the faster 3.0Ghz Kentsfield and Clovertown, and the knowledge that Penryn could remove a lot of Clovertown's deficiencies. The launch clock speeds are very much up in the air though. AMD had originally said 2.3 in Q3 and 2.5 in Q4 for quad core. However, that seems to be when they believed that Intel would stop at 2.66 on quad core. There is no doubt that Intel's 3.0Ghz speed puts pressure on AMD to move higher. However, what AMD might be capable of delivering is anyone's guess. There are some pretty good indications that AMD could launch 100Mhz higher with 2.4Ghz instead of 2.3 and then go to 2.6Ghz in Q4. However, Intel could match this with a 3.0Ghz Penryn and then followup in Q1 or Q2 with 3.33Ghz. So, even if AMD bumped the speed to 2.8Ghz in Q1 or Q2 they could still end up trailing.

AMD doesn't have many bright spots but they do have some. Their integrated chipsets seem to be working okay and their mobile chipsets seem reasonably competitive. AMD should be able to do a lot of volume in the mid to low end desktop with both DTX and its chipsets and with mini-DTX. However, the desktop has lower margins than either mobile or server and this is the low half of the desktop. This does seem reminiscent of 2002 when AMD was hanging on by selling K7 against the lower performing Celeron. In fact, mini-DTX versus mini-ITX is exactly this kind of mismatch with mini-DTX having more memory and memory bandwidith, more expansion capability, and more cpu power. This should at least help AMD hold on in the 2nd half of 2007 if they can do modest mobile sales and gain back some position in servers. Obviously though, AMD has no real chance of challenging Intel on the desktop until they can deliver some real volume in 2008 and by that time they will be up against Intel's 45nm Penryn. AMD should be fine in 4-way and higher servers after Barcelona is finally released. AMD can probably claim the fastest desktop with QFX if Intel doesn't match with its own dual socket system. Intel could very well retain the title of fastest single socket system.


While Intel seems on track and only has to make small steps with Penryn and Nehalem it looks like AMD is going to have to work a lot harder to get back into the game. There are potential gains for AMD but none of them are going to be easy. If AMD works hard and stays on track they could be in a more competive position with mobile, graphics, and high end server by mid 2008. However, since Nehalem's performance is an unknown AMD could find itself with a much tougher high end server competitor in 2009 without ever having gained signficantly in either high end desktop or low end servers. Time will tell.

182 comments:

Heat said...

Thoughtful article very nice work Scientia. Finally an AMD person who is willing to see the whole side of things instead of insisting that everything is still ok with AMD.

Looking forward to seeing AMD get their stuff together and show us some benchmarks and a solid product end of this year.

Hopefully they will run their mouths less and let their engineers work more till Barcelona comes out.

Intel Fanboi said...

AMD's biggest problem is that they don't have any leeway to make any mistakes. Barcelona, R650, 45nm transition, and the reorg all have to go well for them to survive. This puts them in a tenuous position.

gdp77 said...

Finally an AMD person who is willing to see the whole side of things instead of insisting that everything is still ok with AMD.

He was insisting everything was ok until very recenlty. Now his comments is that "AMD will not go BK in 2007". Well scientia, AMD will probably go BK Q1 2008. This is because they delayed barcelona. The only thing that can save AMD now is to pray to God.

Seriously,

IF

a) barcelona will release in Q4 2007 (Christmas)
b) performs significantly better than C2D (I doubt it)
c) Penryn will be delayed at least 1-2 quarters (not a chance)

THEN

AMD will survive

ELSE

AMD=BK.

Call me Intel fanboy, call me whatever u want. There is no way AMD will tolerate more losses. AMD has nothing to sell up to Q1 2008. Therefore AMD will lose more than 500$ per Q, until they will go BK.

Erlindo said...

As Always, nice writing Sci.

What has me thinking is that after reading the whole article, I've noticed that you're concerned about Barcelona's availability.
"If" AMD "could" get enough volume of K10s in shcedule, they could once again reclaim performance leadership in high-end desktops, servers and mobile computing (with Griffin and Puma) until Nehalem appears.

Do you have any info about AMD's upcoming Shangai and Montreal cores? If I'm not wrong, these cores will contend against nehalem until AMD releases Fusion (or K11).

sharikouisallwaysright said...

In the EMEA-Region AMD has grown in the servermarktet by 60% from a low q4/06 up to 300 Mio Dollar in q1/07 with a still growing demand as forecast.

Link to german ZDnet:
http://www.zdnet.de/news/business/0
,39023142,39154745,00.htm#feedback

Scientia from AMDZone said...

gdp77

"He was insisting everything was ok until very recenlty."

I changed my mind. After two delays on R600 plus Fuad's comment that AMD is going to make some fixes in the GPU design for R650 tells me that graphics are behind.

The later release dates for Barcelona plus what appears to me to be a compressed schedule for Phenom suggests that AMD's currently demoed chips are Alphas.

So, I'm less optimistic.

Scientia from AMDZone said...

As far as what kind of leeway AMD has this depends a bit.

The DTX and mini-DTX systems can use existing X2 Athlons so these should move forward after mid year whether Barcelona is ready or not. AMD's integrated graphics chipsets and their mobile offerings also seem okay. So, if AMD can avoid losing additional server share they could probably cut the Q3 loss to $300 Million. Add $300 Million to a $500 Million loss in Q2 and that only leaves about $600 Million to spare. With no other change, bankruptcy would be pushed back to mid 2008.

However, Barcelona should make a late Q3 release which would help with server share. And, if Phenom is available for December then this will help some with desktop share in Q4. This could cut the Q4 losses to perhaps $150 Million. This is also true because the fixed R650 chips should be out by then. This would push back bankruptcy to end of 2008.

If AMD can make it to Q3 2008 they should have time to release the R700 graphics, the new mobile processor, and the 45nm versions of K10. These should be able to compete with Penryn in terms of mobile, high end server and low end desktop (if Intel doesn't respond to the DTX and mini-DTX standards).

The low end server market and upper desktop market are more of a question. Dual core C2D's don't suffer from the quad core MCM problems so it is more difficult for AMD to get ahead. AMD should be reasonably competitive on quad core server and desktop. I can't say whether this will be sufficient to match Nehalem since very little is known about it.

If AMD can make it to Q2 2008 they will begin to get benefits from having two similar 300mm FABs. 45nm is supposedly on track for mid 2008 but a one quarter slide wouldn't surprise me. With 45nm AMD does close some of the process cost gap with Intel.

I have no idea if AMD intends to pursue high K on 45nm in 2009 or if AMD intends to pursue the FinFet on 32nm. I also don't know what might potentially be in K11. Hopefully AMD will share more on these things in June.

Wise lnvestor said...

Scientia, ummm you been reading these 1
, 2 article about K10 and Barcelona?

Those are desktop parts and they seem to be on schedule for late Q3 release. Yes I know they present a gloomy picture for the desktop portion of AMD.

I have heard rumors of Barcelona delay from geek.com and Digitimes on May 16 and 17. While geek.com provided more confusion than fact. But have you read this PC Magazine article? Few days ago I found it on the doc's blog. It's a analysts meeting on May 21 with Tom Sonderman, AMD's director of Manufacturing Technology. Seems to me that quad-core Opteron processors,"Barcelona" is on schedule and in volume for mid year release.

Could the pre-order server part ramp and normal server part orders help AMD go back into a profitable quarter in Q3?(if no delay are expected)

On the graphic side R6xx should at least compete with nvidia's 8xxx. But I think the real ace is the R670's ability to go dual gpu and eventully go Quad crossfire. (And yes they are late...) I have yet to know anything of a counter measure from nvidia. Or am I too optimistic?

Thanks for your analysis and looking forward for your reply.

Heat said...

On the graphic side R6xx should at least compete with nvidia's 8xxx. But I think the real ace is the R670's ability to go dual gpu and eventully go Quad crossfire. (And yes they are late...) I have yet to know anything of a counter measure from nvidia. Or am I too optimistic?

Between quad crossfire and 4x4 i hope AMD will be shipping nuclear reactors to power these things as well. Not to mention a thermal controlled chamber to keep all that cool.

Heat said...

Kinda funny to see a company that was touting the importance of efficiency, energy saving and performance per watt now going the total opposite way as they see fit and their fans acceptance of it is even funnier. Almost as funny as AMD working on MCM when they were bashing it all the time Intel was doing that.....

ck said...

The MCM thing, maybe it's FUD, and maybe it's just the rumours/speculations as usual from the Inq/FUD as in FUDzilla, so what are you yelling at? Yell at developing products is absolutely pointless.

AMD only touts its processors being energy efficient, but ATI and NVIDIA did not say with their GPUs (in fact, HD 2900 XT runs cooler and consumes less power than 8800 GTX when not in full load :\), so what the hell are you yelling again?

Pointlessly and repeatedly yell at something do not make you smarter, just makes you being dumber than a dinosaurs (sorry, I insulted a them, please bear with me).

gdp77 said...

scientia, now that we agree that AMD is in deep shit, I have some questions. So please anyone can give me some answer please do so:

1) Was barcelona delayed because it is an underperforming chip (compared to C2D) or there are design issues? Do we have any info on this? Because if it doesn't perform as good as we were told so, then nothing can help AMD now. I really hope they are dealing with design issues.

2) Was AMD aware of the potential R600 problems when they merged with ATI ? I mean was the R600 failure calculated in AMD's plans or not?

3) There are many "steam processors" (or however they are called) in R600. Any chance that Barcelona could make use of them on a hardware level? (that would be an ace in AMD's sleeve).

4) When barcelona be released, is AMD prepared to sell the chip at dirt cheap prices? Because Intellers will be able to upgrade to quad cores at killer prices in the mid summer. Is AMD, after those big losses, ready to fight a price war in order to regain market share?

more questions to come later...

Scientia from AMDZone said...

wise investor

Recent comments were August and September rather than July for Barcelona. Again, maybe AMD will firm this up in June.

gdp77

"1) Was barcelona delayed because it is an underperforming chip (compared to C2D) or there are design issues?"

All of the architectural changes to K10 seem reasonable. There doesn't seem to be a problem, like with Williamette for example. Presumably, they just missed some bugs in the last revision.

"2) Was AMD aware of the potential R600 problems when they merged with ATI ? I mean was the R600 failure calculated in AMD's plans or not?"

My guess is that the R600 problems were known and that this was one of the reasons for the merger. I think ATI is now getting design help from AMD but is playing catchup to nVidia.

"3) There are many "steam processors" (or however they are called) in R600. Any chance that Barcelona could make use of them on a hardware level? (that would be an ace in AMD's sleeve)."

Stream type cpu processing is in the plans but that would be late 2009 at the earliest.

"4) When barcelona be released, is AMD prepared to sell the chip at dirt cheap prices?"

No. Barcelona is a server chip.

"Because Intellers will be able to upgrade to quad cores at killer prices in the mid summer. Is AMD, after those big losses, ready to fight a price war in order to regain market share?"

Okay, you must mean Agena versus Kentsfield. Kentsfield takes a big hit in performance so Agena should be okay. However, this will get a lot tougher in 2008 with the desktop version of Penryn.

Scientia from AMDZone said...

heat

MCM does cause performance losses; this is why Conroe is a true dual core design. The losses are still there in Kentsfield and Clovertown which are winning simply because AMD has nothing to compete with, not because they are great designs.

AMD has talked about MCM for both GPU and for octal core. These are both to reduce cost. A GPU in the same package is cheaper than two separate chips but should perform the same. MCM for octal core is because there isn't enough market for these chips to make native octal development worthwhile.

What you should be asking is how Intel would make an octal chip. You can't stuff four Woodcrests into one package (even with 45nm) because the additional bus loads would kill the performance. Perhaps Nehalem is a native quad design.

Scientia from AMDZone said...

I commented earlier that I thought AMD was doing okay with mobile. Here's a link that seems to support this:

AMD in about 20% of Toshiba notebooks

So, I'm assuming that AMD will be able to hold onto its mobile share.

enumae said...

Scientia
So, I'm assuming that AMD will be able to hold onto its mobile share.

There are articles pertaining to this announcement and they are talking about a summer release of products (back to school).

This 1 - 1.25% potential market share gain will not help what AMD has already lost in Q1 2007 (4 points), or could possibly lose in Q2 2007 due to the release of Intel's Santa Rosa Platform.

While the news is good for AMD that they got Toshiba to start using there chips and chip sets, two questions come to mind...

What kind of pricing is Toshiba getting?

If they are getting good pricing, what kind of impact will that pricing do to AMD's Q3 revenue?

Thanks.

-----------------------------

Also I have compiled a few projections pertaining to K10 and Penryn.

Here is the link.

I look forward to your opinion.

Heat said...

MCM does cause performance losses; this is why Conroe is a true dual core design. The losses are still there in Kentsfield and Clovertown which are winning simply because AMD has nothing to compete with, not because they are great designs.

That would be true but a company cant cry about MCM and then go around and do the same thing when its convenient to them i am just calling AMD on its BS.

AMD has talked about MCM for both GPU and for octal core. These are both to reduce cost. A GPU in the same package is cheaper than two separate chips but should perform the same. MCM for octal core is because there isn't enough market for these chips to make native octal development worthwhile.

The same can be said about quad core with the limited amount of programs it has for the consumer desktop arena. BY the time octal core is needed Intel will be ready if not before AMD...which has usually been the case......

What you should be asking is how Intel would make an octal chip. You can't stuff four Woodcrests into one package (even with 45nm) because the additional bus loads would kill the performance. Perhaps Nehalem is a native quad design.

You are rite about nehalam it will be native quad core. As for octal chips at present time desktop consumer are not even on dual cores yet left alone octal cores server side mite be a different story. Quad cores have been out for 8 months or so and RITE NOW still a niche high end market which intel is hoping to bring to the mainstream and till there is a big advantage for people to move above quads i dont see anyone really lining up for octals.

Infact i dont think anyone save for maybe dasickninja has quad cores with most still using single or dual core cpus in this blog so octal cores is just AMD showing off another powerpoint slide.....after all its easier to make a powerpoint slide than an actual processor......

I am not going to believe a word AMD says unless i see something real their powerpoints and roadmaps are full of holes, lies and delays........

Roborat, Ph. D. said...

Scientia,

i believe i just answered your cost-per-die question in my recent blog:
Bad Economics

Scientia from AMDZone said...

enumae

"This 1 - 1.25% potential market share gain will not help what AMD has already lost in Q1 2007 (4 points)"

Losses don't occur in one quarter; if AMD's share drops further in Q2 or is still down in Q3 then it is a loss. For example, AMD's apparent share bounced up and down a lot in 2000 and 2001. And, even at AMD's lowest point in 2002 they recovered significantly in just one quarter.

" or could possibly lose in Q2 2007 due to the release of Intel's Santa Rosa Platform."

What is currently being suggested is that Intel will lose mobile share in spite of Santa Rosa. We'll see.

"If they are getting good pricing, what kind of impact will that pricing do to AMD's Q3 revenue?"

Well, AMD is claiming that their revenues for Q2 will outperform Intel and that their gross margins will increase from Q1. If this has any truth to it then the Q1 numbers were a temporary dip rather than an actual loss. An increase in margin would make sense as AMD shifts more production to the 300mm 65nm FAB 36. This would not likely mean that AMD would make a profit in Q2, just a reduction in losses (I'm still figuring about -$500 Million).

For your chart, the best estimate that I could come up with is that K10 at 2.8Ghz matches Penryn at 3.33Ghz. However, Penryn would be about 15% faster if the data is SSE intensive and the code is compiled to use SSE4 instructions.

If I'm understanding AMD's ISSCC numbers then 3.0Ghz should be possible on 65nm as a 120 watt part; 2.8Ghz would be the highest 95watt part.

Scientia from AMDZone said...

roborat

Thanks for showing the calculations. I can now tell what the problems are with your estimate. I left you some suggestions to get a proper estimate.

enumae said...

Thanks Scientia.

core2dude said...


What you should be asking is how Intel would make an octal chip. You can't stuff four Woodcrests into one package (even with 45nm) because the additional bus loads would kill the performance.

Sure you can--you just have to add a separate bus arbitrator (internal bus vs external bus). This is exactly what Intel did with Dempsy--so I woudn't be surprised if something like this is already cooking with Penryn. Internal/External bus relieves bandwidth pressure, but adds latency. However, for most workloads, the latency can be hidden using intelligent prefetchers. And with Penryn's monsterous cache, Intel could be pretty aggressive with prefetching.

You can bet that Nehalem is native quad core.

Aguia said...

Roborat, Ph. D.,
while your analyze is not bad, but it lacks 65nm, where Intel will stand for some time (years) even when introduces 45nm processors.

Also lacking there, is the others versions of AMD and Intel processors.
AMD will have:
-quad core processors
-dual core processors with L3
-dual core processors without L3
-single core processors

AMD will have 4 different cores all with different die sizes.
Intel will have the same for everything which has some advantages and disadvantages.

So your analyze is based on the fact that Intel only does 45nm processors and quad cores processors which is obvious wrong. And that AMD will only manufacture quad cores processors which is also obviously wrong.

If your analyses is just compare quad cores penry with quad cores Barcelona than it’s not real scenario analyze and does leave much to say, or to add. Maybe the only thing good there (acording to your analyse) is to know that Intel can offer about 2X lower prices over AMD when regarding quad core processors.

Benefits of a dual die quad core processor

First quad core in 4Q 2006

The only benefit (to the consumers) of Intel way to do quad cores is price. I’m expecting that Intel quad core will cost me 2X less over AMD, like they did with the Pentium D (~120$)VS Athlon X2 (~290$). If not I don’t see the point of non native quad cores, if we dont win with that.

abinstein said...

heat -
"third party benchmarks are all i care about..."

Apparently you don't care about SPEC_rate, or you'd have known a few simple facts:

1) K8 scales better than Core2 to 4 cores and above
2) At 4 cores, K8 already has comparable integer throughput to Core2
3) At 4 cores, K8 has 25% better float-point throughput than Core2
4) At 8 cores, no Core2 system is actually faster than K8

Wanna proof? Here are the facts from publicly available, repeatable, 3rd party benchmarks that you claim to care about but apparently not.

Conclusion is Core2 is for personal enthusiasts and entry-level servers.

core2dude said...

It remains to be seen how Intel fares on specfp_rate with the 1600 FSB, bigger cache, and improved FP unit of Penryn. My guess is, they will come within spitting distance of Barcelona.

Erlindo said...

Excellent blog Abinstein.

I really appreciate that great analysis you've made. Didn't know (until now) that C2D really SUCKS when it comes to processor scaling.

Keep the good job and please post some more hard facts about these topics.

abinstein said...

"Funny how SPEC_rate is suddenly the most important benchmark in the world according to AMD fanboys."

You don't need to like SPEC at all, but over the past 15 years or so it has been the most used benchmark to measure processor microarchitecture improvement, by both the industry and academia.

Of course, for your PC, whatever application you use will be more accurate measurement. The problem of using those is it's generally very difficult to reproduce the same benchmark results, and they are very easily affected by using a different dataset for the benchmarking.

Anyway, my claims are based on SPEC and cover the same things as SPEC do. I have no claim outside the SPEC coverage (which is CPU+memory). But if you choose not to recognize the facts within the coverage domain, then you are just the type of fanboys yourself was talking about.

Heat said...

I did not read your blog i just went with the comment you posted. But i and most of the readers here are not running 2p or 4p servers. Infact I and probably even you are typing up this thread on a single socket desktop in which C2D without a doubt is the unequaled king. I could care less what it does in server space since i dont maintain one nor am i looking to purchase one in the near future.......all i and most people on tech sites care about is the consumer market space and let the corporations worry about the rest.......

Azmount Aryl said...

heat said...
You sir are the biggest idiot not only do you have a comprehension problem since i was not talking to YOU nor was i talking about core 2 duo vs K8 BUT almost all the benchmarks are won by core 2 duo.


Actually your statement is incorrect. Core2Duo has about 15% better performance at the same clock speed, however Athlon's available in higher clock speeds than Core2Duo (2.93GHz vs. 3.0GHz favoring AMD on dual core system and 2.66GHz vs. 3.0GHz on quad core systems favoring, again, AMD). Don't try to mislead readers, thats just silly.

Scientia from AMDZone said...

core2dude

Yes, Intel used a hybrid internal bus design for Tulsa. I'm thinking we won't see that again though. Intel is talking about 1600Mhz for the FSB which shouldn't be too bad compared to AMD's 2133Mhz. Presumably Intel will use two native quad Nehalems MCM to get octal.

Scientia from AMDZone said...

heat

Tone down the flames and personal attacks. Obviously Azmount is wrong about the clock speeds but getting a clock speed wrong isn't some kind of AMD fan conspiracy. A simple correction will do.

Scientia from AMDZone said...

Secondly, let's dispense with the arguments about argument form and semantics.

Scientia from AMDZone said...

Now, to get things back on track. I think it is clear that AMD's current 65nm X2's will be fine on mini-DTX and probably good enough on DTX as well.

By the time we get up to the ATX form factor though I would have to give C2D the advantage.

AMD should get some help with dual core versions of K10 but not until Q4 so this still gives Intel a fair amount of lead.

The server situation which Abinstein was referring to changes a bit more quickly in Q3 and there is no doubt that even with a quad FSB chipset Intel will not be competitive with anything over dual socket until Nehalem.

core2dude said...


Presumably Intel will use two native quad Nehalems MCM to get octal.

Nope! It should be better than that. But they might do an MCM first just for the time-to-market, and then come up with the real thing. You know, CSI/HT is not so good when it comes to MCM. Either one core has to always jump across a CSI/HT link, or you end up with two CSI/HT jumps for every core.

Remember, with Polaris, Intel has demonstrated that it can put building blocks together with complicated core-to-core routing. Larrabee will be massively multi-core, validating these technologies in the real market.

In case AMD comes with K10 MCM 8-core, Intel may come with Penryn 8-core using internal vs external bus and MCM. The real problem there would be, they may not be able to fit 8 cores in the 771 package. The rumor I had heard was that they could fit only 3 dies in there (at 107 mm^2, just the die area of four dies is 428 mm^2, or 2cmx2cm--just about the size of the heat-spreader).

AMD will also face similar problem with K10 MCM 8 core until they move to 45nm. They will have to accomodate about 500 mm^2 of die area in Socket F. I don't know if that is feasible.

With NHM, Intel anyway changes the socket. So they might be able to come up with a socket large enough to hold NHM MCM 8 core. But again, if AMD has no competing product, they may not do it.

core2dude said...


The server situation which Abinstein was referring to changes a bit more quickly in Q3 and there is no doubt that even with a quad FSB chipset Intel will not be competitive with anything over dual socket until Nehalem.

Why is that? Because Hector said so? Or did Randy Allen say that Barcelona is going to blow away anything that Intel has to offer?

The fact is, no one has seen what Tigerton is capable of doing. We don't know what its FSB is going to be (Intel demoed 1333 last year, but Inq has it that it will be 1066). And more importantly, hardly anyone uses quad-core for spec_fp. TPCC is the name of the game, and Core2 has soundly defeated K8 on that front. Even Tulsa offers better performance, though it burns 170 watts per socket.

If Intel could manage 1333 FSB with quad-core Tigerton, the game could be very close.

Also, Nehalem is a Big Big deal. And it is much much closer than what AMD wants you to believe.

I really hope AMD has something in works (by something, I mean a new uarch) for 2009 timeframe. Otherwise, the future looks really bleak.

Scientia from AMDZone said...

core2dude

AMD's octal would be on 45nm after mid 2008. HT isn't perfect but remember that HT 3.0 is already much faster than CSI will be and it is possible that AMD could bump the speed further inside the package. The extra speed will help with the extra hop. Also, in mid 2008 AMD gets a big connectivity boost with 8 HT links per chip. I doubt this will be enough for K11 though so I assume AMD will need to put some kind of switch directly on the chip.

Scientia from AMDZone said...

core2dude

"The fact is, no one has seen what Tigerton is capable of doing."

Okay, the problem with Tigerton is that it is going to use a lot of power. You really can't get around this when you have one chip driving six memory controllers plus four FSB's while also provided northbridge functions and FSB routing and filtering.

Intel may be able to get Tigerton up to 1600Mhz to make it speed competitive but at such a power draw that it will fall off on performance/watt. There really isn't much Intel can do to get around this problem. Think of Tigerton as an interim solution between dual socket limited Clovertown and unrestricted Nehalem.

"Also, Nehalem is a Big Big deal. And it is much much closer than what AMD wants you to believe."

It's my assumption that AMD intends to compete against Nehalem with 45nm DC 2.0 architecture K10's. I haven't heard yet if there are any tweaks at all to the architecture at this node.

"I really hope AMD has something in works (by something, I mean a new uarch) for 2009 timeframe. Otherwise, the future looks really bleak."

Presumably AMD is working on K11. My guess is this would be after mid 2009. However, maybe AMD will tell us more at the meeting toward the end of July.

core2dude said...


AMD's octal would be on 45nm after mid 2008. HT isn't perfect but remember that HT 3.0 is already much faster than CSI will be

Wrong again! HT 3.0 maxes out at 5.3 GTs, with Barcelona being much lower than that. According to Inq, Nehalem will have CSI at 4.8 GTs and 6.4 GTs. So raw bandwidth wise CSI is much better. HT has some advantages like dynamic split and all, which CSI (probably) does not have. But at 4S, CSI will eat HT 3.0 for breakfast. At 8S, HT may have advantages due to 2x8-bit splitting.

Heat said...

Obviously Azmount is wrong about the clock speeds but getting a clock speed wrong isn't some kind of AMD fan conspiracy. A simple correction will do.

Cool good call clock speed is not a conspiracy i just wanted azamount to realize how wrong his statement was. Would have appreciated you coming in and clarifying the situation before it got out of hand..... kinda frustrating to make someone realize they are wrong and have someone else (abinstein) back them on their wrongness.

My apologies.

Heat said...

A question why wouldn't you totally delete azamount's post about clock speed along with the rest of the posts when it is obviously the wrong info he is giving out???

core2dude said...


Intel may be able to get Tigerton up to 1600Mhz to make it speed competitive but at such a power draw that it will fall off on performance/watt.


I would like to wait and watch. Essentially, Caneland is nothing but two Bearlakes bolted together+few tweaks. So Caneland's power consumption should not be more than twice that of Bearlake. Bearlake+Clovertown is a very competitive platform in performance/watt. So, there is nothing inherent in Caneland that would put it at performance/watt disadvantage.

I don't think Intel will be able to take Tigerton to 1600 FSB without 45 nm. However, typically in MP, Intel does not mind putting huge caches (24M?) to compensate for the lack of bandwidth.

Nehalem should be extremely good at MP. But I really doubt how big of a market 4P is going to be if both Intel and AMD introduce 8-core for DP systems. A DP, 8-core Nehalem platform will have 32 hardware threads. There are very few workloads today that need anything more than that.

Scientia from AMDZone said...

core2dude

"Wrong again! HT 3.0 maxes out at 5.3 GTs, with Barcelona being much lower than that."

Even today, the term "GT/sec" has not been defined by Intel. In order to reach your conclusion of higher speed you have assumed that GT/sec is the equivalent of Ghz. It would seem a bit odd for Intel to use GT/sec instead of Ghz if that is what they meant. And, contrary to your assertion the term, "GT/sec" is not used by the HyperTransport consortium. They use either Ghz or GB/sec.

CSI was started back when HT was version 1.0 and even as late as December 2005 the INQ said categorically that CSI was slower than HT. I do find it interesting that HT 1.0 had a speed of 6.4GB/sec and it would not surprise me if Intel matched this speed.

However, it would surprise me a great deal if not only had Intel managed to match the speed of HT 3.0 but (as some conclude by assuming GT/sec means Ghz) Intel actually managed 3-5X HT 3.0's speed. I don't find that likely at all.

Until Intel actually defines what GigaTransfer/sec means there isn't any to tell if it is faster.

core2dude said...


CSI was started back when HT was version 1.0 and even as late as December 2005 the INQ said categorically that CSI was slower than HT. I do find it interesting that HT 1.0 had a speed of 6.4GB/sec and it would not surprise me if Intel matched this speed.

By that logic, K10 was started in the days of Pentium 4, so it should not match the performance of C2D.

Without going into any specifics, I have resons to believe that the numbers (4.8 GTs and 6.4 GTs--yes GTs and not GHz) posted by Charlie of Inq are correct. In general, Charlie has his facts straight. And that is why, I still believe that Barcelona will reach 2.9 GHz immediately after introduction, and won't top at 2.6 GHz.

Scientia from AMDZone said...

core2dude

That is my point. Intel gave the speed of CSI in GT/sec while the HT consortium gives the speed of HT in GB/sec. There isn't any way to know how to convert one to the other.

The two basic theories are:

1.) That GT/sec is the same as Ghz. If this is the case then CSI would be at least three times as fast as HT 3.0.

2.) That GT/sec is the same as GB/sec. If this is the case then CSI is about twice as fast as HT 1.0.

I find #2 more likely. However, it is possible that GT/sec refers to something else.

sharikouisallwaysright said...

From german PCGH:
http://www.pcgameshardware.de/?
menu=browser&mode=article&article_i
d=602643&entity_id=-
1&image_id=658658&page=1

Calculation from Nvidia about ASP of low end ATI-GPU and Memory, Boardprice.

Maybe someone is interested...

savantu said...

Scientia said :

That is my point. Intel gave the speed of CSI in GT/sec while the HT consortium gives the speed of HT in GB/sec. There isn't any way to know how to convert one to the other.

The two basic theories are:

1.) That GT/sec is the same as Ghz. If this is the case then CSI would be at least three times as fast as HT 3.0.

2.) That GT/sec is the same as GB/sec. If this is the case then CSI is about twice as fast as HT 1.0.

I find #2 more likely. However, it is possible that GT/sec refers to something else.


This shows how little you know.

GT/s is a perfectly fine way to measure an interconnect without revealing important info.

To calculate BW you need to know the link's width , that is how much bytes it can transfer at once.

If CSI is 8bit/1Byte wide and runs at 6.4GT/s you have a BW of 6.4GB/s ...Yipeee!
If it's 128bit wide you have 102.4GB/s.

Scientia from AMDZone said...

savantu

"If CSI is 8bit/1Byte wide and runs at 6.4GT/s you have a BW of 6.4GB/s "

Yes, assuming Intel is using the term GT/sec the same as it is used with SCSI interfaces then 6.4 GT/sec could be 12.8 GB/sec since 16 bits (2 bytes) is the most likely width of CSI. However, 12.8 GB/sec would be slower than 20.8 GB/sec.

Four 16 bit CSI links would require 256 pins on the new socket.

enumae said...

Scientia

There is a PDF presentation (page 31) talking about Larrabee and Gesher, CSI is labled as 17GB/s/link.

Could you elaborate on this.

core2dude said...


Yes, assuming Intel is using the term GT/sec the same as it is used with SCSI interfaces then 6.4 GT/sec could be 12.8 GB/sec since 16 bits (2 bytes) is the most likely width of CSI. However, 12.8 GB/sec would be slower than 20.8 GB/sec.


Time for a tutorial on interconnects.

Intel's 1600 MHz FSB is actually 400 MHz. But it is quad pumped (two clocks, offset from each other by 90 degrees, one bit opportunity per edge per clock). That makes it a 1600 GTs bus (you see, 1600 MHz is a misnomer). Now this bus is 8 bytes wide. So the net bandwidth is 12.8 GB/s. Note that, the bus is bidirectional, and hence this is the bandwidth. There is no such thing as a unidirectional bus.

CSI should be a point-to-point unidirectional interconnect (just like HT), with one link in each direction. So, if you have 16-bit wide links (which most likely it will be), the bidirectional bandwidth is 6.4GTs x 2bytes/direction x 2 directions = 25.6 GB/s of bidirectional bandwidth. Most likely, Intel will play the same quad pumping trick to actually clock it at 1600 MHz and achieve 6.4 GTs.

HT 3.0, on the other hand is, 5.2 GTs x 2 bytes/direction x 2 directions = 20.8 GB/s. This way, CSI will have about 25% bandwidth advantage at 6.4 GTs. At 4.8 GTs, it will have a disadvantage of about 9%. It should be noted that HT 3.0 supports upto 32 bit links, and hence, it is possible to have 41.6 GB/s bidirectional bandwidth with HT 3.0. But that requires a socket change. Also, wide links tend to be inefficient (that is one of the many reasons why Intel FSB sucks compared to HT 2.0, even though they have equal theoretical bandwidth).

However, the raw bandwidth does not mean much without the protocol. HT 1.0 and HT 2.0 were extremely efficient, since they did not include any error correction. The clock speeds were so slow that they could afford to send packets over HT link without any error correction (expected one error over 100 yrs). However, HT 3.0 will run at the blazing clock speed of 2.6 GHz (unlike FSB, HT is dual pumped, not quad pumped, so the clock speed is half the GTs count, as opposed to 1/4th for FSB). So the probability of errors is non negligible. Consequently HT 3.0 introduced error correction. But it is kind of clumsy, since it is an add-on feature, an afterthought, you may say. And hence, the protocol is not that efficient in its error handling. Intel, on the other hand, has been using ECC for FSB for a long time. Also, for all practical purposes, Intel defined PCIe, which pervasively uses ECC. So CSI should have very well thought out ECC implementation.

The physical link latency of CSI/HT is negligible (speed of light, about 1nS per foot). The real latency arises from the CSI/HT complex that drives it--and that complex is not governed by the standard. Everyone implements it on their own. So, it is too premature to judge the latency of CSI vs HT at this point. One rule of thumb, each hop adds at least 25 to 30 nS. For K8 on HT 1.0, this figure was about 50 to 65 nS. AMD's HT 3.0 implementation should improve on this quite a bit.

To summarize, CSI should be between -9% to +25% of HT 3.0 as far as raw bandwidth is concerned. However, this means little without knowing the details of the protocol. Arguably, Intel knows the HT protocol in and out (because of its standard nature), however, AMD knows very little about the CSI protocol. So Intel has a little bit of "intelligence" advantage.

Enjoy!

core2dude said...


There is a PDF presentation (page 31) talking about Larrabee and Gesher, CSI is labled as 17GB/s/link.
Could you elaborate on this.


It is not clear what a "link" means here. If it is bidirectional link, it would put Gesher CSI implementation at 4.2 GTs, which sounds kind of low for 2010 timeframe. If it is unidirectional link, it puts it at 8.4 GTs, which is not impossible if Nehalem achieves 6.4 GTs.

At this point, very little is know about CSI. All that I have is Charlie@Inq's article claiming CSI to be running at 4.8 and 6.4 GTs. Even though I have very high regard for Charlie (afterall, all the things that he talked about Larrabee turned out to be true). However, we just have to wait and see to know for sure...

core2dude said...


Four 16 bit CSI links would require 256 pins on the new socket.

???????
What the heck? What field are you using for your multiplication? I don't know of any finite/infinite field in which this calculation is valid (although, you could use field isomorphism to make it valid, somehow)...

abinstein said...

core2dude -

"Intel's 1600 MHz FSB is actually 400 MHz ... (you see, 1600 MHz is a misnomer)."

No, 1600MHz is not a misnomer. The clocks are only at 400MHz, but the data bits can switch as fast as 1600MHz.


"if you have 16-bit wide links (which most likely it will be), the bidirectional bandwidth is 6.4GTs x 2bytes/direction x 2 directions = 25.6 GB/s of bidirectional bandwidth."

A link with bi-directional 1-bit capability has to be 2-bit in width. There is no way to carry 16 bi-directional bit streams (i.e., 32 aggregated bit streams) on only 16 lines. Thus the correct calculation for 16-bit wide 6.4GT/s CSI bandwidth should be 12.8GB/s


"HT 3.0, on the other hand is, 5.2 GTs x 2 bytes/direction x 2 directions = 20.8 GB/s."

A 16-bit wide HT 3.0 clocked at 2.6GHz achieves 20.8GB/s in one direction (not two). In terms of GT/s, it is 5.2GT/s times dual-pumped times 16 bits (2 bytes), also 20.8GB/s.


"This way, CSI will have about 25% bandwidth advantage at 6.4 GTs. At 4.8 GTs, it will have a disadvantage of about 9%."

CSI does not get bi-directional transfer on single lane if PCI-e doesn't. Thus the 16-bit CSI at 6.4GT/s will be slightly faster than HT 2.0. The 4.8GT/s CSI will be slightly slower than HT 2.0.


"Also, wide links tend to be inefficient (that is one of the many reasons why Intel FSB sucks compared to HT 2.0, even though they have equal theoretical bandwidth)."

This is wrong. FSB sucks not because it is wide, but because it is a shared, multiple accessed medium where arbitration frequently interrupts transfer. Comparing FSB to HT 2.0 is also wrong. First, FSB is a parallel but HT is serial; second, FSB carries most memory traffic but HT 2.0 has nothing to do with memory bandwidth; third, on cHT links, inter-processor communication occurs by itself, whereas on FSB it must share access with memory and IO activities.


"(unlike FSB, HT is dual pumped, not quad pumped, so the clock speed is half the GTs count, as opposed to 1/4th for FSB)."

As I said above, it is apple to orange to compare a serial protocol such as HT to a parallel one such as FSB. Compared to PCI-express, 8 lanes HT @1.4GHz offers 5.6GB/s, whereas 8 lanes PCI-E @2.5GHz offers less than 5GB/s!


"Consequently HT 3.0 introduced error correction. But it is kind of clumsy, since it is an add-on feature, an afterthought, you may say. And hence, the protocol is not that efficient in its error handling."

I have no idea what error handling efficiency you are talking about. An error control block is just 4 bytes in size. You put it either in packet header/tailer or as user-defined format.


"Intel, on the other hand, has been using ECC for FSB for a long time. Also, for all practical purposes, Intel defined PCIe, which pervasively uses ECC."

First, the HT-to-FSB comparison is totally wrong, as I have said above.

Second, CRC of PCIe will reduces the net data rate further. To limit the effect, a large packet must be used, thus increase transfer latency.

Third, there is nothing that would prevent HyperTransport to use any type of error control in a user-defined packet.


"So CSI should have very well thought out ECC implementation."

Duh...


"The real latency arises from the CSI/HT complex that drives it--and that complex is not governed by the standard. Everyone implements it on their own."

You are not understanding it right. For starter, HT has 20% lower latency and 20% higher bandwidth than PCIe because HT has a clock forwarding scheme which explicitly supply the clock signals, whereas PCIe encode/decode clock signals within the data stream.

HT has even lower latency also because its lower packet overhead (8-12 bytes versus 20-24 bytes of PCIe at the physical layer).

HT has further lower latency due to its priority request interface, where devices requiring lower latency service can ask for it during a (potentially long) transmission of other devices.


"So, it is too premature to judge the latency of CSI vs HT at this point."

Again, if you believe CSI is going to base on PCI-e on physical/link layer, then your comments here are totally fanboistic.


"Arguably, Intel knows the HT protocol in and out (because of its standard nature), however, AMD knows very little about the CSI protocol. So Intel has a little bit of "intelligence" advantage."

Knowing a good algorithm in and out doesn't necessarily allow you to device a better algorithm.

abinstein said...

"There is a PDF presentation (page 31) talking about Larrabee and Gesher, CSI is labled as 17GB/s/link."

As I've said many times, Intel in the end is a marketing company. It is the master of great-looking roadmap maker. Look at how much it actually accomplished from history... only the Moore's law, and nothing else!

Azmount Aryl said...

Wow Abinstein, don't be so cruel to this fine young intel employee.

Greg said...

"Clueless."

Apparently you are savantu.

"the data bits can switch as fast as 1600MHz."

Or in other words, for every high point on the square wave 2 bits can be sent while the low points can send 2 bits as well. Thus, 4/cycle x 400 Million cycles/sec = 1600 Mhz.

"Even if it is serial?" Essentially yes, because you have to have communication bothways. You can't send data back and forth over one single line of communication.

"Clueless take 2 : HT is parallel."

No, you seem to be fairly clueless. No interconnect has ever been truly serial. Even the serial connection had 9 pins, only 4 of which were grounds. Serial and parallel are essentially relative terms to describe whether or not an interface has a large number of bits/cycle sent or a low number. HT is an 8 bit/cycle interconnect, so it is relatively serial. However, there are still 8 simultaneous/parallel bits being sent.

"Why don't you shut up instead of spewing crap ?"

Why don't you quit trolling.

"You're pathetic"

Oh great argument there... Wait a second, it wasn't one.

Greg said...

Actually, I made a mistake. There have been many truly serial connections, but we use very very few anymore.

core2dude said...


abinstein blurbed ...

A link with bi-directional 1-bit capability has to be 2-bit in width. There is no way to carry 16 bi-directional bit streams (i.e., 32 aggregated bit streams) on only 16 lines. Thus the correct calculation for 16-bit wide 6.4GT/s CSI bandwidth should be 12.8GB/s

... and a lot more ...

Strongly recommend you read HT specification. Being clueless is not a ways of sounding intelligent. Try to understand what a unidirectional link means. What bidirectional bandwidth means. HT is a unidirectional link, and HT consortium always advertises bidirectional bandwidth of 32-bit links (i.e., 64 lines).

And by the way, there are numerous ways of using one wire in full duplex mode (e.g., using orthogonal carriers), and you will find those out if you decide to go for a college degree. However, these techniques are not very useful at the frequencies at which CPU interconnects operate.

All that aside, 2.6 GHz HT link is 5.2 GTs due to dual pumping. You cannot further multiply 5.2 GTs due to dual pump. By that standard, I would have to multiply 6.4 GTs of CSI by 4. Just being able to write a blog or puke out some idiotic garbage online does not make you sound intelligent or expert in the area. You need to have basic education in the area to discuss the topic intelligently. First read about HT, specs of which are available online.

Yes, PCIe and HT are fundamentally different in clock forwarding vs clock inferring. However, the reasons go much beyond latency. PCIe has to go over long distances. Clock skew at these distances can be pretty bad. So PCIe uses clock infering (or "AC coupling"). That adds to latency, but not too much. And by the way, HT 3.0 gives AC coupling option specifically at long distances (HT 1.0 and 2.0 did not give these options). Again, there are many ways of achieving AC couping, one of which is what Ethernet uses (where level transitions are guaranteed at every clock boundary). HT AC coupling also uses similar methodology. Another method is to use clock inference using Fourier analysis without guaranteeing any bit transition order (this is what Plysiosynchronous Digital Hierarchy uses). However, those techniques result in significantly higher latency and jitter. But I am sure you won't understand any of this because you do not have basic educational qualification to understand what a Fourier transform is.

The bottom line is, I know what I am talking about. You need college education (preferably graduate) to comprehend that. So go hide under the rock whence you came from, for, your ignorance is exposed.

core2dude said...


Or in other words, for every high point on the square wave 2 bits can be sent while the low points can send 2 bits as well. Thus, 4/cycle x 400 Million cycles/sec = 1600 Mhz

I repeat, MHz is a misnomer. This is because, you have 4 x 400 = 1600 million bit opportunities, but that does not mean that there needs to be a bit transition at that boundary. In fact, with probability half, there would not be a bit transition at a bit opportunity, and hence, the waveform will remain flat. This implies that, on average, there will be two bit transitions every four bit opportunities. In other words, in one second, on average, you would have 800 million bit transitions, bringing the mean frequency of the wire to 400 MHz. Of course, this is not perfect, and you will have a lot of places where the bits transition at every bit opportunity. To figure out the exact expected frequency, more detailed probabilistic analysis would be needed. However, I just wanted to make the point that the mean frequency of the data line is a lot less than 1600 MHz. This is important because that is what finally determines the mean error rate.

abinstein said...

savantu -
"Clueless take 2 : HT is parallel."

As others have said it's comparative. HT can have as few as 2 CAD lines to as high as 32 CAD lines, whilst FSB or PCI can only be their full size. The sheer ability to serialize transmission on fewer # of lines make HT serial in my previous comment.

The HT consortium regard HT as parallel because its clock & misc control signals are sent in parallel to the CAD signals.

Still, even in this definition the core2dude's comparison between HT and FSB is wrong.

core2dude -
"2.6 GHz HT link is 5.2 GTs due to dual pumping. You cannot further multiply 5.2 GTs due to dual pump."

5.2GT/s is probably the dual-dump result. Still, a 16-bit link of 2.6GHz HT 3.0 has 20.8 GB/s aggregated throughput. Currently 16-bit HT 2.0 at 1GHz has 2.0GT/s and 8.0GB/s throughput. You do the math.

If CSI achieves 6.4GT/s then by literal comparison it does have about 23% higher BW than HT 3.0.

savantu said...

In other news , Barcelona slips even further causing Cray to miss revenue forecast for 07.

Looks like the real problem with Barkie is bugs which hinder validation , bugs need new steppings , which of course take more time.

http://biz.yahoo.com/iw/070604/0261144.html

T800 said...

In other news , Barcelona slips even further causing Cray to miss revenue forecast for 07.

This is starting to get a little bit scary. I had a hunch that Barcelona was going to slip all the way until Q4-2007, now that is looking more and more likely.

Pop Catalin Sever said...

Henri Richard sells AMD shares

http://www.forbes.com/feeds/ap/2007/06/04/ap3786531.html

Just before the launch of Barcelona? and Computex? That can't be good, he's a business man he knows that if Barcelona performs share price will rise even before Barcelona will be available in volume...

Pop Catalin Sever said...

Working url
http://www.forbes.com/feeds/
ap/2007/06/04/ap3786531.html

Scientia from AMDZone said...

enumae

I've looked through your link but I can't find Larrabee, Gesher, CSI or 17GB in the document. The searches come up empty.

Scientia from AMDZone said...

core2dude

"Time for a tutorial on interconnects."

Your "tutorial" wasn't particularly informative. I have no idea why you are trying to compare CSI with the Intel FSB. It is well known that CSI was developed from PCI-e so making assumptions like quad pumping is a bit silly. Basically, it sounds like you are trying to invent the perfect fairytale spec for CSI.

A more reasonable expectation would be something a bit faster and with reduced latency from the current fastest PCI-e spec. We know that one of the goals of CSI was to reduce the very high latency of PCI-e.

Scientia from AMDZone said...

savantu, t800, pop catalin

I tried to find where either AMD or Cray said that Barcelona was late as you are claiming but I couldn't find that. All I could find was speculation by a third party:

"Cray recently became aware that there has been a delay in volume parts availability for a key component of the quad-core XT4 until later in (the fourth quarter)," wrote Northland Securities analyst Chad Bennett in a note to investors. "We believe the most logical key component is the quad core processor from Advanced Micro Devices Inc."

So, in reality Chad Bennett is guessing that Barcelona is late. This is not the same as an announcement from Cray.

Ho Ho said...

scientia
"I've looked through your link but I can't find Larrabee, Gesher, CSI or 17GB in the document. The searches come up empty."

That is because you were late and the .pdf has been updated in the mean time. Try this google cached HTML version instead and scroll down to page 17. The nubmers are there, though without the pictures. Originally there was a 4P system with 17GB/s links between each socket.


As for the Cray, what else besides CPU can it be that it doesn't let them create their machines?

Ho Ho said...

here is a screenshot from that PDF before the updating and you can see both CSI throughput and latency there, as well as few Gesher details. That image has also been removed from the PDF for some reason.

core2dude said...

A more reasonable expectation would be something a bit faster and with reduced latency from the current fastest PCI-e spec. We know that one of the goals of CSI was to reduce the very high latency of PCI-e.

PCIe is fundamentally limited in its ability to provide coherency. Intel is trying to put lipstick on that pig with PCIe 2.0 extensions, but there are limits. PCIe is designed for (relatively) long-haul interconnects with delay-tolerent devices in mind. That is why, its efficiency at small packet-sizes is extremely bad. At the same time, neither HT nor CSI would be able to match it at large packet sizes. So designing CSI from PCIe would require redefining most of the protocol anyways (memory reads/writes tend to be 4 to 8 bytes). To add to that, I don't think CSI will encode clock. Why would you encode it, if all you care about is transmitting it across 6 inches? The overhead of clock-encodig at that point is not justifiable. So from that perspective, CSI should be closer to FSB.

As far as quad-pumping is concerned, that was just a guess. Achieving 6.4 GTs with dual pumping across a motherboard sounds too optimistic (though, I don't know how frequency and distances are related, so it may very well be possible). But then, for all we know, Charlie is just shooting from the hip, and CSI would be limited to 4.2 to 4.8 GTs. In that case, as HT 3.0 shown, dual pumping is possible.

The bottom line is, I do not know how much better or worse CSI is going to be compared to HT 3.0. But from the figures floating around, it sounds to be within 25% of HT 3.0 (better or worse).

savantu said...

Scientia said :
I tried to find where either AMD or Cray said that Barcelona was late as you are claiming but I couldn't find that. All I could find was speculation by a third party


Reading comprehension problems ?

Try again :
http://biz.yahoo.com/iw/070604/0261144.html

Ho Ho said...

Good news! I found the original PDF from my temporary files and have uploaded it here. Most notable are pages 17 and 31.

enumae said...

Another source believes that AMD's Barcelona will be delayed to September or October.

Link.

Dr. Yield, PhD, MBA said...

Scientia wrote:
I tried to find where either AMD or Cray said that Barcelona was late as you are claiming but I couldn't find that. All I could find was speculation by a third party:

But lets look at what we do know:
1. Cray announced that XT4 would be shipping late due to availability delays in a "major" component.
2. Cray's product page (http://www.cray.com/products/xt4/index.html) shows no major architectural differences between xt4 and the currently shipping xt3 other than AMD's 4core CPU.
3. AMD has been touting the socket compatibility of Barcelona with Opteron, so (2) seems like a viable product (quad core update to existing platform).

So based on the known details, and that Cray is not claiming difficulties in shipping the XT3 product, what component would you have us believe is the issue?

This is HORRIBLE news for AMD, and I for one am sad to see it. They are executing as well as Intel was 2 years ago. The difference is that they don't have the buffer of a big checkbook and brand equity to tide them over until they regain focus. Very disturbing...

abinstein said...

core2dude -
"Probably it was so technical that you were not able to digest it fully."

Actually it was so full of technical errors that he probably doesn't care to read.

The only thing that you got it right was 16-bit HT 3.0 has 5.2GT/s. This is something a highschool can browse and find out. Most if not all of your other arguments, from the comparison of FSB to HT, to the claims on error correction designs, are just wrong.

abinstein said...

Ho Ho -
"As for the Cray, what else besides CPU can it be that it doesn't let them create their machines?"

I thought Intel has millions of x86_64 compatible quad-cores processors waiting for sales. Oh, I forgot, those are for clueless "enthusiasts" to spend $$$ and screw themselves. ;-)

Seriously, Cray must be desperate for more Barcelona chips. It is anticipating Cray XT4 deliveries in Q4, and their acceptances and revenue as late as Q1 next year. In other words, Barcelona would've been handed to Cray in volume before Q4.

The problem really isn't on AMD, but on the nature of Cray's work. To make one system, it needs to assemble hundreds of processors and boards, test every part of it, deliver to its customer, and allow it to be tested before the transaction is considered done. A "slip" of Barcelona volume availability from early Q3 to late Q3 would've delayed Cray's revenue from Q4 to early Q1 next year.

On the other hand, AMD claims Barcelona systems will be shipping from partners in Q3.

core2dude said...


The only thing that you got it right was 16-bit HT 3.0 has 5.2GT/s.

Clearly demonstrates lack of comprehension! Pity!!!

One grammatically correct sentences with three correct numbers that does not mean anything! How remarkable!!! Typical blog owner without basic understanding of the subject...

abinstein said...

core2dude: "Yes, PCIe and HT are fundamentally different in clock forwarding vs clock inferring."

We already know that.


core2dude: "However, the reasons go much beyond latency."

Latency is not the reason, but the consequence.


core2dude: "PCIe has to go over long distances. Clock skew at these distances can be pretty bad. So PCIe uses clock infering (or "AC coupling")."

Which is why HT consortium says HT is not a replacement for PCIe.


core2dude: "And by the way, HT 3.0 gives AC coupling option specifically at long distances ... HT AC coupling also uses similar methodology."

We already know that, too. You don't need to side-track discussion this much to hide your previous errors.


core2dude: "Another method is to use clock inference using Fourier analysis ..."

So much for you to start a discussion on totally unrelated stuff. If these are what you know, then go write them down in your diary. Don't come here and babble about FSB "efficiency" or error correction that you don't understand correctly.


core2dude: "The bottom line is, I know what I am talking about."

Just start talking about some things that you do know doesn't change the fact that your previous statements are plain wrong. Let me correct them again here -

* Compared to FSB, HT has higher efficiency not because FSB is wider, but because HT is point-to-point while FSB is shared medium.

* Compared to PCIe, HT has much lower latency not because of complexity, but because of 1) efficient header, 2) clock forwarding, 3) priority request interface, among other things.

* There is no error correction in FSB or PCIe like you so proudly claimed; those CRC bytes only do error check. Neither does HT3 have error correction, but error check.

* HT3 defines a simple but effective error-retry protocol down into the link layer. You totally make up the inefficiency, probably from the very ignorance you talked about.


core2dude: "You need college education (preferably graduate) to comprehend that. So go hide under the rock whence you came from, for, your ignorance is exposed."

I'm really not sure who needs hiding. I at least acknowledge an error; not like some people just try to cover up by talking about irrelevant things. College education is probably a waste of money for them.


core2dude: "I repeat, MHz is a misnomer. This is because, you have 4 x 400 = 1600 million bit opportunities, but that does not mean that there needs to be a bit transition at that boundary."

That does allow 1600MHz bit transition frequency. The FSB speed is calculated on the clock of the transceiver, which must handle 1600 million bits per second per line.


core2dude: "I just wanted to make the point that the mean frequency of the data line is a lot less than 1600 MHz. This is important because that is what finally determines the mean error rate."

No, the bit transition frequency has little to do with FSB error rate, which for the most majority doesn't even happen on the transmission lines, but on the transceiver (which can't switch fast enough - to 1600MHz!). A lower bit transition rate, however, saves power in proportion.

abinstein said...

core2dude: "Would you be kind enough to point out the errors?"

See my other comment above.


"Or your ability to punch on the keyboard and post on the blog sites makes you an absolute authority on the subject that cannot be questioned?"

You seem to have big opinions on my blog even without reading it. My suggestion is go clock on my profile and take a look there. BTW, I have no authority on anything other than my analyses. Go read and confront my analyses, not my personal. As long as you don't make personal attacks or bring up pointless arguments, I will respond you.

core2dude said...


See my other comment above.

Saw them. Mostly you keep on blabbering about how you already know the stuff (though you clearly do not).

It appears that you not only have problem understanding technical stuff, you also have problems with basic English comprehension. For example, when I say "one of the reasons why FSB is inefficient is its width" you seem to infer that I am claiming that to be the only reason. When I talk about ECC/EDC, you pick out only ECC.


You seem to have big opinions on my blog even without reading it.

Been there done that. All you have is your baseless opinions of the world. It is not even entertaining (as opposed to Sharikou's blog).


No, the bit transition frequency has little to do with FSB error rate

Einstein!!

core2dude said...


Don't come here and babble about FSB "efficiency" or error correction that you don't understand correctly.

I can write a book on ECC/EDC, and on the finite field math on which they are constructed. So "understanding" is not my problem. I should have said EDC to being with, but said ECC (which by the way, is generically used for ECC/EDC), which I changed in later posts. But that does not make any of the arguments invalid.

The fact is, HT did not have any protection in 1.0 and 2.0 (which was the main point, before you sidetracket it by nitpicking on ECC vs EDC--which again is semantics problem, not a fundamental error), which PCIe/CSI have always had that.

Riddle me this, if you have a 64 bit bus, how much would you waste, if you were to send a 12-byte transaction (hint: 25%)?

The problem is, you do not know where 5.2 GTs comes from. You do not know how BW of HT link is calculated. And you think, by writing long replies you appear intelligent.

enumae said...

Clarification from AMD...

Barcelona on time, Budapest delayed.

However, Budapest shipments to Cray slipped. "Specific to Cray, we did have a change in our schedule, as far as when Cray gets Budapest parts," Hughes said, declining to share further specifics.

Link.

abinstein said...

core2dude -

I can fully understand your anger because I burst your bubble and revealed how wrong you were. Here unfortunately I have to do the same again.


"When I talk about ECC/EDC, you pick out only ECC."

In no where were you talking about "EDC". You've been talking about error correction in PCIe & FSB as if it would increase their efficiency. Quite the contrary in fact, and I only want to point that out (oops, have to burst your bubble again). What determines efficiency is not CRC codes, but the re-transmission protocol. Besides, ECC is not error correction codes, but error control codes.


"Been there done that. All you have is your baseless opinions of the world."

Baseless to the point that you can't counter technically, but have to resort to personal attacks and bad mouthing? What you are saying here is truly baseless.


"I can write a book on ECC/EDC, and on the finite field math on which they are constructed.

Good, before you write such a book, be sure to get it right - the CRC codes used in PCIe, FSB, or HT3 have nothing to do with the latters' efficiency. If you can't even comprehend/admit this, then understanding is apparently one of your problems.


"The fact is, HT did not have any protection in 1.0 and 2.0 (which was the main point, before you sidetracket it by nitpicking on ECC vs EDC"

No, the main point is that you were implying the added CRC capability in HT3 would make it less efficient than those in PCIe and FSB. I sidetrack only to point out how clueless you are.


"The problem is, you do not know where 5.2 GTs comes from. You do not know how BW of HT link is calculated."

I was wrong about 5.2GT/s. Thanks for pointing that out. But I feel sorry if you think BW calculation is some arcane knowledge and others have difficulty to know how to do. You are just kidding yourself.

Scientia from AMDZone said...

ho ho

You haven't posted an apology yet. Why are posting comments?

Wise lnvestor said...

enumae. Thanks for posting the link to put all those (nasty) rumors to rest.

I see wind in my sails...

Wise lnvestor said...

And I would like to point out that there are lot of financial analysts from numerous institutions who had no idea what are they talking about.

Most of the time, they don't do any real research, to the point that's almost criminal.

Here a link from the Inq. On Saturday 16 September 2006, 18:02

There a interesting summery about the "delayed" part for Cray code name "Budapest".
The Q4/07 part is called Budapest, and it is the Barcelona core with HT3.0 in 12xx Opteron and A64 guise. The core should be done well within the alloted time frames, but its introduction may be delayed due chipset availability. Basically, this is the first major update to HT, and people may miss windows.

But as "Budapest" is scheduled for Q4/07 release,(so Cray can finally get to sell XT4 in Q1 08) then technically is on time.

Scientia from AMDZone said...

savantu and core2dude

Both of you, dial it back, NOW.

Savantu, there is nothing wrong with my reading comprehension. I read your link and it does not say what you are suggesting. Why are you pretending that it does? And, why do you have the silly idea that including an insult with your pretense makes it more truthful? The truth is that you are wrong and you are being rude.

Core2dude, if you don't want to post here that is fine. If you keep throwing out insults that is where you are going to end up. Again, including insults with your arguments does not make them any more accurate. The truth is that Intel has not yet specified the actual top speed of CSI in GB/sec and I have no idea why are pretending that you know. You are guessing and that is quite different.

Ho Ho said...

scientia
"You haven't posted an apology yet. Why are posting comments?"

I'm just trying to help because it looked like as you don't know how to use google to verify the data you were given.

To repeat enumae, can you elaborate on the data in that PDF?


"Both of you, dial it back, NOW."

I've got a bright idea, why not ban them? After all they have done much worse than I did!

abinstein said...

Ho Ho -

Aside from the fact that you still owe scientia an apology, there's really not need for you to find that pdf. enumae gave a perfectly working link to the presentation.

enumae -

The Labrrabee "tera-scale" solution, on the processor level, looks just like SUN's Niagara (or maybe Rock); they just change the orientation of the processor cores. On the system level, it looks just like Opteron. In short, if SUN makes its UltraSparc line socket-F compatible, you'll get something like this as early as 2nd half this year. If this is truly what Intel's going after, then AMD's (long-term) outlook cannot be better.

Pop Catalin Sever said...

http://www.dailytech.com
/article.aspx?newsid=7554

So far Barcelona barely reaches 2.0 GHz and the demo was with 1.6 GHz cpu's.

Something is wrong here and I can't find and explanation why this is like this.

Scientia would you care to comment on this please. I know this has happened throughout history more or less but I don't know exactly what were the consequences.

Ho Ho said...

abinstein
"enumae gave a perfectly working link to the presentation."

Problem with the link was that there was the updated PDF with some information removed. Compare the two yourself if you don't believe me.

Scientia from AMDZone said...

I wasn't aware that Cray was waiting for Budapest but I suppose HT 3.0 speed would help with their interlink. That Budapest will be out in Q4 is not exactly a secret. The INQ talked about this in September of 2006: INQ.

Barcelona will have HT 1.0 while Budapest is the second version with HT 3.0. Originally, HT 3.0 wasn't supposed to be released until 2008. Budapest was orignally supposed to have HT 2.0 but AMD moved 3.0 up.

Wise lnvestor said...

Is not your fault Scientia. It's those financial analyst. All they got is a rumor of a AMD quad core been delay. But they didn't dig deeper to find out the whole truth.

I for 1 don't know what Cray was after before I finish reading enumae's Link.

I'm glad this clear things up.

Pop Catalin Sever said...

core2dude

we are perfectly fine without you commenting or educating anyone, really!

Now take your personality disorders somewhere else.

Scientia from AMDZone said...

ho ho

I understand. You want to post here but you have too much pride to apologize. I gave you the chance to be a man but the shoes were apparently too big for you. Your links were helpful though and I guess you have a few years yet to mature. So, keep wearing your Keds and I'll leave your posts up.

Scientia from AMDZone said...

Core2dude. You have the wrong idea about comments here. I don't have to agree with the comments and the comments do not have to favor AMD. For example, Dr Yield gave a very good argument about Cray's delay. It's an inferred but solid argument and there are no insults. What I don't understand is why that pattern seems to be so difficult for some to follow. Just leave off the insults and you can disagree all you want.

You also have the wrong idea about Ho Ho. Neither his knowledge nor intelligence nor his stance on Intel are an issue. The only issue was being called a liar on my own blog. He and Heat routinely insult me on roborat's blog and I suppose I should just ignore that since they are not being disruptive here.

Red was a bit different. I've never regretted banning Red because he was disruptive but contributed very little. Others like Ho Ho do contribute once you separate the wheat from the chafe.

However, what I will avoid are blogs like Sharikou's, 180's, and Roborat's where there are lots of trolls, lots of insults, and far less substance. I don't need 50 comments of "me too", "X sux", "you're an idiot", or calling everyone who disagrees a fanboy.

Sharikou is what he is. He is like the people who look for for bigfoot, the loch ness monster, or aliens. Sharikou cannot except the notion that AMD won't prevail. That is why he cherry picks the news and often exagerates the significance of each item. However, in all fairness, both 180 and roborat do the same thing. The only difference is that Sharikou is pro-AMD while 180 and roborat are pro-Intel.

The only really balanced news blog I've seen is "Tracking AMD" which posts both good and bad AMD news. If someone had the same thing for both good and bad Intel news that would great.

Heat said...

http://www.dailytech.com/article.aspx?newsid=7554

One vendor demonstrated Barcelona to DailyTech running at 1.6GHz. Current AMD Barcelona samples are not scaling too well. AMD partners confirmed the highest running, POST and OS capable, Barcelona processor is 2.0 GHz. AMD previously posted benchmarks of a simulated 2.6 GHz Barcelona.

Looks like we wont be seeing a 3.0ghz barcelona after all like you claimed scientia.....stock or overclocked.........

As far as insulting you scientia you have to admit your recent predictions have been waaaay of base..... I call things like i see it....i will also be the first to tell you if something you do is correctly assessed for example the first post on this thread.............though they are still mine and your opinions and we dont always have to agree......

If come tomorrow i start touting with out any facts or truths except a speculated performance on a slideshow by the manufacturing company how barcelona will get knocked out by the celeron i would welcome people calling me a fanboi as well.....thats just the way it goes.....

I always notice that if someone says something misguided about intel which sheds a positive light on it you are very quick to interject and correct it but if an AMD fan does the same thing you let things slide.....not very unbiased of you.....

Pop Catalin Sever said...

Quote Legit Reviews :
"The V8 Penryn test system at 3GHz scaled nicely against the dual-core and quad-core 3.33GHz Penryn processors as well at the Core 2 Extreme QX6800 quad-core processor. AMD wouldn't comment on the record on what their upcoming Barcelona processor would score, but people in the know said that AMD is getting ~16,000 with a pair of their Barcelona processors on Cinebench 10. If this proves to be true and you keep in mind that the 45nm Penryn V8 system is underclocked right now and scoring ~23,000 on the same benchmark it means things could get interesting really soon."

http://www.legitreviews.com
/article/521/1/


Things certainly look bad for AMD right now, but I guess we can draw more conclusions when Barcelona finally launches.

If AMD won't be able to charge a premium for Barcelona over Penryn the .45 nm volume of Intel will put so much pricing pressure on AMD that it will be the end of it.

Poke said...

http://www.dailytech.com/Quick+and
+D...rticle7574.htm

"We had the opportunity to benchmark the AMD Barcelona, native quad-core on an early stepping. We only had a few minutes to test the chip, but we were able to run a quick Cinebench before we were instructed to leave.

The AMD benchmark ran on a single-socket, K10 CPU running at 1.6 GHz on NVIDIA's nForce Professional 3400 chipset. According to the system properties, the AMD system used 4GB of DDR2-667.

The most similar Intel system we could muster up on such short notice was an Intel Xeon 3220. The Xeon X3220 is clocked at 2.4 GHz, and ran on Intel's Garlow workstation chipset (Intel X38). This system property profile stated the system utilized 4GB of DDR2-800.

Cinebench completed the default benchmark in 27 seconds for the 1.6 GHz K10; 17 seconds for the Intel Xeon X3220. The Kentsfield Xeon was 58% faster with a 50% higher clock frequency for Cinebench.
"

Care to comment Scientia?

Erlindo said...

pop catalin sever wrote:
Things certainly look bad for AMD right now, but I guess we can draw more conclusions when Barcelona finally launches.


Have in mind tahat these are 1.6GHz Barcelonas running on DDR2-667 vs intel's 3GHz penryns running with DDR2-800 or probably DDR3 modules. :-D

Heat said...

Have in mind tahat these are 1.6GHz Barcelonas running on DDR2-667 vs intel's 3GHz penryns running with DDR2-800 or probably DDR3 modules. :-D

Read around a lil bit and you will notice that your point at best is moot.......far cry from the 40% over clovertown BS that AMD was mouthing off.....Also to note AMD is having troubles clocking their latest past 2.0Ghz so to compare it with a 3.0+ Ghz penryn is laughable. At this rate Intel might as well do what AMD did with its X2 and raise their clockspeed by 10s instead of 100s mhz at a time...

If the barcelona is at linear scaling it still loses no matter what its clockspeeds to a one year old technology core 2 duo.......almost like the 2900XT losing to a six month old technology.......quite the track record AMD is setting the only thing they are good at is releasing slideshows so that fanbois can drool over them..........

Poke said...

AMD is having troubles clocking their latest past 2.0Ghz so to compare it with a 3.0+ Ghz penryn is laughable. At this rate Intel might as well do what AMD did with its X2 and raise their clockspeed by 10s instead of 100s mhz at a time...

Yea, scaling is terrible on K10s from the looks of it. Comparing a K10 to a 3GHz Penryn is a joke for Intel. Intel might as well cancel Penryn if K10 isn't even competitive with the existing Kentsfield/Clovertown.

The POV-Ray results are consistent with the Cinebench results. K10 offers little performance boost over K8 in FP intensive applications.


http://www.legitreviews.com/article/521/1/

V8 3GHz Penryn scales very nicely compared to a quad 3.33GHz Penryn.

Ho Ho said...

poke
"And don't even bother with the DDR2-800 vs. DDR2-667 argument, memory bandwith doesn't make much of a difference in Cinebench."

Even if bandwidth would make a difference then AMD would still have an advantage as it has much better efficiency than Intel and even with lower clocked memory it still has more bandwidth availiable.

Scientia from AMDZone said...

Okay, earlier. I said:

"Four 16 bit CSI links would require 256 pins on the new socket."

This is correct and I have no idea why Core2dude thought it was wrong or resorted to insults. Both PCI-e and HT uses two wires per bit and a separate pair for send and receive. Presumably so would CSI. So, PCI-e and HT require 4 wires per bit and these would be connected to 4 pins. If we assume 16 bits that would be 64 pins per CSI link. Four CSI links would then require 256 pins. 16 X 4 X 4 = 256. AMD will also need 256 pins for the data portion of four HT links with DC 2.0 so these two are similar.

Although PCI-e 2.0 does allow for 32 lanes this doesn't seem likely because Intel's Socket B has 1366 pins compared to 1207 for Socket F for AMD. That is a difference of only 159 pins while doubling the CSI width would require another 256 pins.

The current top speed for PCI-e 2.0 is 5Ghz with 8GB/sec/direction. This would be a maximum dual direction transfer of 16GB/sec.

The speed given in the Larrabee diagram of 17GB/sec would only slightly higher than 16GB/sec so this wouldn't be a surprise. Basically, if you bump the speed from 5Ghz to 5.3Ghz you would have 17GB/sec.

The big question is whether or not Intel has managed to bump CSI from PCI-e's 5Ghz to 6.4Ghz and drop the 8/10 encoding. So, I guess I would have to agree with Core2Dude that this is possible. With 8/10 encoding this would be almost identical to HT 3.0's speed and without 8/10 encoding it would be about 28% faster than HT 3.0.

It might seem more likely that Intel would keep the 8/10 encoding since the same link would also be used for I/O and we know that they have plans to route Geneseo through the northbridge. Even so, it would match HT 3.0.

There are two other significant differences though. The first is that HT only uses half the header size of PCI-e. This tends to make HT more efficient for shared memory (cache coherency). However, it is possible that Intel could use an abbreviated header for CSI.

The second difference is that HT is physically a daisy chain while the indications are that CSI will still use a switching hub like PCI-e. This makes a 4-way motherboard considerably more complex because the hub has to accept and route 20 CSI links (four for each processor plus four I/O). However, this would have less effect on a single or dual socket board (only six CSI links on dual socket). There is also some suggestion that Intel will keep the FSB and northbridge on single socket Nehalem systems.

Scientia from AMDZone said...

heat

I've never said that 3.0Ghz for K10 quad was likely in 2007. In fact, I said it was unlikely. If you are going to disagree with me then try to disagree with something I actually said.

As far as AMD's having trouble clocking over 2.0Ghz you are simply wrong (and Poke, you won't get very far jumping in to agree with someone who is wrong).

AMD has K10 quad currently clocking to 2.4Ghz without any trouble. If you'll recall, AMD said originally that K10 quad would be released at 2.3Ghz in Q3 and then 2.5GHz in Q4. However, with the good 2.4Ghz speeds I'm thinking that will be the release speed although others have suggested AMD will bump the release speed up to 2.5Ghz but I'm not saying that since I haven't heard firm information about current 2.5Ghz clocks. However, this would logically then mean 2.6 or 2.7Ghz in Q4.

Repeating what I said earlier, AMD needs 2.8Ghz to roughly match Penryn at 3.33Ghz. Also, by the ISSCC data, it looks like K10 quad would top out at 3.0Ghz with 120 watts on 65nm with 2.8Ghz being the fastest 95 watt part. This certainly suggests that anything faster than 3.0Ghz will require 45nm for AMD.

poke

The cinnebench scores for K10 are in the same performance/clock ballpark as C2D. I have no idea what the cinnebench code was compiled with but I know that K8 loses about 20% when running on Intel compiled code. Also, AMD never bothers to tweak its demo systems and we have no idea how these two compare in terms of motherboard, OS, drivers, etc.

If you really want to pin all your hopes on this score plus the Pov-ray score then I wish you luck because you and Heat are basically trying to squeeze water out of a stone.

Finally, stop the insults; they are not called for.

Ho Ho said...

scientia
"The second difference is that HT is physically a daisy chain while the indications are that CSI will still use a switching hub like PCI-e. This makes a 4-way motherboard considerably more complex because the hub has to accept and route 20 CSI links (four for each processor plus four I/O)."

Are you sure that HUB is required? On page 17 there is a diagram and there is no such hub. There is something called ICHn that seems to be doing what northbridge does in current motherboards and it is connected to a single socket with an additional 17GB/s CSI bus

Scientia from AMDZone said...

erlindo

You got the two articles mixed up. The cinnebench scores are very slightly (5%) in Intel's favor. However, this could certainly have been pointed out without all the rudeness. And, they are quite correct that the memory is not a factor. At 1.6Ghz K10 wouldn't need the same bandwidth as C2D quad running at 2.4 or 2.66Ghz.

pop catalin and poke

Yes, V8 looks like it could very well keep QFX from taking the top spot. Intel could retain the title of ultimate gaming system.

Scientia from AMDZone said...

ho ho

No, I don't know the specifics of Larrabee. With the diagram that was posted earlier by the INQ for a quad Nehalem system it was stated that Intel used a third party switch to connect CSI. Larrabee's architecture reminds me of a GPU since it seems to show the same dual racetrack buses.

The larrabbe diagram looks a lot less complex than the all connected Nehalem diagram. I suppose it would be possible to put the switch on the northbridge if it no longer has to access memory.

abinstein said...

"V8 3GHz Penryn scales very nicely compared to a quad 3.33GHz Penryn."

On a Cinebench 10 which nobody knows what or how it benchmarks, V8 indeed seems impressive.

In reality, any inter-socket communication is going to kill its performance twice (once for the communication itself, once for reduce memory/IO bandwidth).

Pop Catalin Sever said...

"Yes, V8 looks like it could very well keep QFX from taking the top spot. Intel could retain the title of ultimate gaming system."

Not gaming, neither V8 or Quad FX are gaming systems, simply because games don't require 4 or 8 cores to run and neither do they take any benefit from that so far.

V8 is primary a workstation setup, and with that kind of difference Intel will push AMD's top bin Barc. CPU's into mainstream pricing category like is happening now with FX series.

In fact not only top bin CPU's will be under pricing pressure but the whole product line. Not to mention the aftermarket halo effect of having the performance leadership that will put all Intel products under the spotlight while AMD's CPU's won't see any favorable reviews from anyone... important (like TH,Anand etc).

AMD won't escape pricing pressure until it manages to retake performance leadership and that combined with decent manufacturing volumes. I don't see that happen in the near future unless AMD manages to pull a rabbit from the hat.

Erlindo said...

pop catalin sever wrote: V8 is primary a workstation setup, and with that kind of difference Intel will push AMD's top bin Barc. CPU's into mainstream pricing category like is happening now with FX series.

Current FXs yes but not Phenom FX. We don't have any hint of how well Phenom FX (or Barcelona) will perform. Maybe, it could be intel's offerings the ones that could be pushed into mainstream category. ;D

Erlindo said...

Scientia:

The article I was talking about was the one where intel was demoing V8 with penryn CPUs clocked at 3.0GHz

In no moment I was referring to the other article in which Barcelona loses a merely 5% even with an intel compiled program like Cinebench

Scientia from AMDZone said...

Okay, in the legit review mention of the cinnebench penryn scores we can see nearly perfect scaling of 99%. However, rather than showing that Penryn is a great processor this tends instead to show that cinnebench isn't stressing the processor very much. Any type of bus loading would fall off a lot more than 1% even on K10.

If you'll recall, even Smithfield did well with Cinebench so it wouldn't surprise me if they use the Intel compiler. I think you will find that when we get to something more substantial like cryptography that Penryn's impressive performance will vanish.

Heat said...

As far as AMD's having trouble clocking over 2.0Ghz you are simply wrong (and Poke, you won't get very far jumping in to agree with someone who is wrong).

AMD has K10 quad currently clocking to 2.4Ghz without any trouble.


http://www.dailytech.com/article.aspx?newsid=7554

THis is what the article states: One vendor demonstrated Barcelona to DailyTech running at 1.6GHz. According to engineers familiar with the chip technology, the current AMD Barcelona samples are not scaling core frequencies well. AMD partners confirmed the highest running, POST and OS capable, Barcelona processor is 2.0 GHz.

Please list any proof of your claim (save for AMD's powerpoints and Inq reports) that AMD has no trouble making a 2.4Ghz cuz so far i have not read anything to prove you are rite.

Just the fact that they are demoing 1.6ghz cpus this late in the game should be some indication so giving some proof instead of saying i am wrong without anything to back it up would be appreciated.....

Erlindo said...

OK, once again here's the quote from the legitreviews article:

AMD wouldn't comment on the record on what their upcoming Barcelona processor would score, but people in the know said that AMD is getting ~16,000 with a pair of their Barcelona processors on Cinebench 10. If this proves to be true and you keep in mind that the 45nm Penryn V8 system is underclocked right now and scoring ~23,000 on the same benchmark it means things could get interesting really soon.

These are 1.6GHz Barcelona processors vs Penryn's 3.0GHz. The author mentions that Penryn is underclocked (to 3.0GHz) because the final processor would be clocked to 3.33GHz. Let's assume for a minute that Barcelona has %100 clock scaling, and if the previous scores are true, then Barcelona will end up with an amazing 32000 score.

Scientia, please correct me if I'm wrong.

enumae said...

Erlindo
These are 1.6GHz Barcelona processors vs Penryn's 3.0GHz.

Where do you see that?

The author mentions that Penryn is underclocked (to 3.0GHz) because the final processor would be clocked to 3.33GHz.

He does?

Please shoe where he says the final processor would be clocked at 3.33GHz.

Let's assume for a minute that Barcelona has %100 clock scaling, and if the previous scores are true, then Barcelona will end up with an amazing 32000 score.

So Barcelona will have clock speeds of 3.2GHz?

Thats better than any of the supposed road maps.

----------------------------

There is no where near enough information to draw any conclusions from this test.

It is all just rumor until there is an actual statement from AMD or third party review.

Scientia from AMDZone said...

heat

Yes, I know how you are interpreting the article. However, this is what the article should say:

According to third party engineers who are familiar with the ES samples that they have received from AMD, their current ES Barcelona samples are slower than actual release speeds. AMD partners confirmed that the fastest ES samples they have recieived run at 2.0 GHz.

Sorry, no proof. However, you state firmly that you don't believe AMD will hit 2.3Ghz in Q3 and we'll see who is actually right.

"Just the fact that they are demoing 1.6ghz cpus this late in the game should be some indication"

Of nothing. I recall one reviewer who had an 800Mhz Conroe system just before release. And, I recall one demo system that Intel had to water cool to get it to clock to release speeds. This is what we are seeing again with the Penryn sample underclocked to 3.0Ghz; it could probably hit 3.33Ghz too with water cooling. Remember, these were ES chips, not final versions. 2.0Ghz on an ES is not unusual. You are trying way too hard to read something into this.

Scientia from AMDZone said...

erlindo

It doesn't say what speeds were used but I'm reasonably sure that we won't see 3.2Ghz K10 quads until 45nm is released.

It depends on what he means by "real interesting". If we do assume that the K10 is running 1.6Ghz then we end up with both systems having a score of 25,000 with Penryn at 3.33Ghz and K10 at 2.5Ghz. A tie would be interesting to me. However, this would seem to contradict the other cinebench scores which suggest that K10 needs to be about the same clock to match Penryn on cinebench.

So, perhaps he just meant that it would be interesting because Intel would be way ahead.

Heat said...

Sorry, no proof. However, you state firmly that you don't believe AMD will hit 2.3Ghz in Q3 and we'll see who is actually right.

Fair enough i think 2.3Ghz MITE be possible but if they are released it will be an equivalent of a paper launch with actual products not in the chain till 2 or 3 months after initial release......so we are in partial agreement...

Of nothing. I recall one reviewer who had an 800Mhz Conroe system just before release. And, I recall one demo system that Intel had to water cool to get it to clock to release speeds.

THat mite be ONE out of a hundred ES samples that were being benchmarked and overclocked the way Core 2 duos overclock rite now so your point is not valid.

How many ES or details do YOU see on the internet about barcelona compared to C2D. I am just going with the ONLY info we have about the barcelona and that is so far they have only displayed 1.6ghz or lower clockspeeds....

This is what we are seeing again with the Penryn sample underclocked to 3.0Ghz; it could probably hit 3.33Ghz too with water cooling. Remember, these were ES chips, not final versions. 2.0Ghz on an ES is not unusual. You are trying way too hard to read something into this.

Comparing C2D speeds and barcelona is also an unfair comparison we already know C2D overclock wayyy over their stock speeds on air not to mention Penryn is not only a die shrink but also includes High K gate which should allow for higher clockspeeds than before...

3.0ghz to 3.33ghz with penryn seems totally possible with the above mentioned information.....But 1.6ghz to 2.3ghz left alone 2.5ghz which was originally announced seems like a more lofty goal given AMD's history in higher clockspeed bins......i guess the AMD hopefuls will see it one way and Intel hopefuls see it another.......i hope you do call it for what it is if AMD does release a 2.3ghz+ version but it is a paper launch because they have been notorious for those recently......

Heat said...

Latest update by extremetech....

http://www.extremetech.com/article2/0,1697,2143301,00.asp

Article states:
That 1.6-GHz figure is true; I received that number from one of AMD's partners, along with my contribution to the story: "disappointing". And that's news, if only because three of AMD's partners used that exact word in describing the chip. One partner used this term: "chaos". And these guys had AMD boards in their booth.

Heat said...

This is a far cry from when C2D chips were first announced and benchmarks. People were questioning the benchmarks if they were fake or real only to eat crow later. Some people to THIS DAY believe that c2d is not the performer it is even though it beats K8 in the same benchmarks that used to be dominated by K8 over pentium 4.......

In any case disappointing and chaos are not the words you would hope your partners will use to describe your newest chips soo unless AMD can pull a miracle in the next two or three months or do what they are famous for and delay barcelona again things are looking rather bleak for AMD and their fanbois........

Erlindo said...

Scientia wrote:It doesn't say what speeds were used but I'm reasonably sure that we won't see 3.2Ghz K10 quads until 45nm is released.

OK, I know that. But the point I was trying to make was that according to the test provided by legit reviews, Barcelona will beat Penryn clock per clock on that intel optimized app called cinebench.

enumae said...

Erlindo

Without knowing the clock speed of the supposed Barcelona score of 16,000, you can't do much in the way of comparisons.

If I remember correctly, all references of the 1.6GHz are relative to the Daily Tech article talking about Cinebench 9.5 (64 bit), nothing about Cinebench 10.

Heat said...

OK, I know that. But the point I was trying to make was that according to the test provided by legit reviews, Barcelona will beat Penryn clock per clock on that intel optimized app called cinebench.

Erlindo i will try not to insult you but it is getting very irritating to see you push the same point that has been debunked soo many times......even by scientia no less....

In the cinebench demo AMD was using a 1.6ghz barcelona and Intel was using a 2.4GHz XEON!!!! NO WHERE IN THERE IS A PENRYN MENTIONED!!!!! ONCE MORE NO WHERE IN THERE IS PENRYN MENTIONED!!!!!!!!!

If barcelona linearly scales that would mean that it will still be 8% slower than the C2D CONROE NOT PENRYN clock for clock......and please for once in your life stop making petty excuses for benchmarks being intel biased.....everything is intel biased till AMD beats them in it then all of a sudden every benchmark is valid again...........

So far we have TWO benchmarks which were AMD released and in both k10 pretty much gets a whooping for all the hype AMD was throwing about..........i would not have been so adamant about this had AMD went the humble route when they knew they had a dud but their continued bragging and talking instead of engineering is getting to me and should get to any fan of performance and technology........

If you really want to pin all your hopes on this score plus the Pov-ray score then I wish you luck because you and Heat are basically trying to squeeze water out of a stone.

Atleast i am pinning my hopes on the two available tangible bits of information we have which comes close to a third party benchmark can i ask you what are you basing YOUR hopes on.......an AMD powerpoint presentation with speculative numbers or Inq links......i guess believing in something tangible is going out of fashion with AMD hopefuls.......

If barcelona comes out as a champ that would be a surprise since all things are pointing to a dud....compare the hype to when C2D was bout to be released and you pretty much know how this party will end.........

abinstein said...

Heat -
"Some people to THIS DAY believe that c2d is not the performer it is even though it beats K8 in the same benchmarks that used to be dominated by K8 over pentium 4."

I'm not sure what people you are talking about, but IMO you have the wrong opinions on two things -

First, K8 is better than P4 not just for better desktop performance. With enough effort a P4 system can match or exceed X2 4800+ (or equivalently, C2D E6400 or better) on desktop apps at lower cost. The problem however is the high power consumption, poor multi-core scalability, and worse server/workstation performance, that eventually make P4 obsolete.

Secondly, there is few people actually deny Core 2 Duo performs better on some (or most) desktop applications that interest enthusiasts. However, to date, it is higher-cost than K8, and scales poorer than K8 to server or multi-socket environment. Thus obviously Core 2 Duo is not better than K8 in the sense that most enthusiasts believe. What is ridiculous is many C2D-loving enthusiasts simply relay C2D's better desktop enthusiast performance to better general performance, which is simply not the case.

If a company needs a dual or quad socket server, it would benefit more by getting a K8 system. At dual-socket, the K8 system will lose to a Core 2 counterpart a bit in integer, but win a bit in floating-point; at quad-socket, the K8 system will beat a Core 2 one on both integer and floating-point. Now, of course, if your company wants a server to encode Windows Media or run Cinebench, then Core 2 will be the better choice.

Scientia from AMDZone said...

heat

"Fair enough i think 2.3Ghz MITE be possible but if they are released it will be an equivalent of a paper launch with actual products not in the chain till 2 or 3 months after initial release"

Well, I agree that that will be one fumbled launch if AMD only manages to get 2.3Ghz out the door in Q4. I'm thinking AMD is going to at least get 2.5Ghz out in Q4 but they might do better.

"THat mite be ONE out of a hundred ES samples that were being benchmarked"

That was a system that Intel was showing. And, I have no doubt that Intel picks the best for its demos.

"How many ES or details do YOU see on the internet about barcelona compared to C2D."

None. Which means that AMD's security is extremely tight.

"so far they have only displayed 1.6ghz"

Those low clocked samples are at least two revisions behind the actual production chips.

"C2D overclock wayyy over their stock speeds on air"

Well, yes and no. Kentsfield will not run even at stock 3.0Ghz speeds with the regular HSF. However, with premium air cooling it overclocks fine.

On the other hand, we both know that top air systems today match water systems from 2003. So, that air claim has been fudged a bit. To claim genuine air today you can't really count higher than a midrange air system.

"But 1.6ghz to 2.3ghz left alone 2.5ghz which was originally announced seems like a more lofty goal given AMD's history in higher clockspeed bins"

The 1.6Ghz chip is not AMD's current best. AMD has 2.4Ghz running now. You are still thinking that AMD cherry picks its best ES chips for demo systems like Intel does.

abinstein said...

"That 1.6-GHz figure is true; I received that number from one of AMD's partners, along with my contribution to the story: "disappointing". "

Surely people will be disappointed when they run a badly optimized binary on the platform.

Those people are not only lazy, but probably doesn't know how to do benchmark properly. Benchmarking is never done by just downloading whatever binary you see on-line and run. Cinebench is compiled for Core Duo. A binary compiled for Core Duo (with icc) can easily hurt K8 by up to 20%, as reckoned by the Portland Group.

Intel actually has a Performance Benchmark group working solely with these software vendors to make its CPU look better on them. In the end Intel's benchmarking efforts are just good cosmetic. What is more interesting is a properly configured SPECint of SPECfp result, and compare that to K8 and Core 2. Maybe K10 will perform just the same as K8 and less than Core 2, or maybe it will outclass both. We don't know until we see it.

Scientia from AMDZone said...

heat

I can't believe you are quoting that extremetech piece. I've seen INQ pieces with more credibility. For example, if this quote:

I heard a "possibly 1.8-GHz at launch"

isn't FUD then I don't know what would be.

Scientia from AMDZone said...

heat

"If barcelona linearly scales that would mean that it will still be 8% slower than the C2D"

The figure I got was 5% slower.

"stop making petty excuses for benchmarks being intel biased"

As I've already mentioned, PGI has a graph (which I can hunt up if you don't believe it) which shows that AMD falls off more with Intel code than C2D does with K8 optimized code. C2D only loses about 10% with K8 optimized code while K8 loses 19% with Intel code. Again, PGI has no reason to lie about this since 3/4 of their market are Intel chips. Also, PGI is clearly not giving any special favoritism to AMD since Intel's processors also run faster with PGI code than they do with Intel code.

"So far we have TWO benchmarks which were AMD released"

No. We have one benchmark which AMD mentioned only as a comparision between quad and dual core which was not intended to be compared with Intel. The second benchmark was sneaked by the reporter and it was most likely Intel code. Secondly, the "equivalent Intel system" score is unlikely to be equivalent.

"can i ask you what are you basing YOUR hopes on"

I'm basing my estimation on an understanding of the engineering changes that AMD has made. Even the K10 Optimization Guide bears out the 2X decoding speed of SSE on K10 over K8. You can read the Guide yourself if you don't believe this. However, I can tell you that the 2X improvement covers 95% of the SSE instructions. I can also say that the doubled buses, doubled prefetch, extra stack hardware, improved branch prediction, enhanced out of order operation, loads over stores, better cache hierachy, greatly optimized memory access, plus far better memory prefetch will make a difference with Integer. These are the same things that increased the IPC of Dothan and C2D.

So, you must either be saying that these architecture changes won't improve performance (in which case you must be in serious need of Thorazine) or you are saying that the current revision is still full of bugs and/or the process is not working well enough to get a usable clock speed. Since AMD has recently denied the second point you must also be claiming that they are lying.

"If barcelona comes out as a champ that would be a surprise since all things are pointing to a dud"

I guess "all things" would include the pro-Intel rumors and what Intel is saying but would exclude what AMD is saying and the pro-AMD rumors. Not really "all things" is it?

"....compare the hype to when C2D was bout to be released and you pretty much know how this party will end......... "

No comparison. Intel was pushing its chip six months before it was released. In contrast, AMD has had the tightest security on K10 that I have ever seen.

Erlindo said...

enumae wrote:
Without knowing the clock speed of the supposed Barcelona score of 16,000, you can't do much in the way of comparisons.

If I remember correctly, all references of the 1.6GHz are relative to the Daily Tech article talking about Cinebench 9.5 (64 bit), nothing about Cinebench 10.


OK, I'll have to half-agree with you on that one, but with the recent info we got, my best guess is that these are 1.6GHz Barcelonas.

Sci, I'd like to know what's your take on this?

Scientia from AMDZone said...

heat

If you believe:

1.) That AMD is lying even though this would be grounds for stock fraud and could get AMD upper management put in prison as well as fined.

2.)That every pro-Intel rumor is true while every pro-AMD rumor is false.

3.) That the Intel Compiler produces good code for K8.

4.) That the architectural changes to K10 compare at all to the handful of changes to Prescott.

5.) That a 1.6Ghz system was the fastest cherry picked chip that AMD could scrape up for Computex.

Then that goes a long way to explain your point of view.

If you don't understand cpu architecture that is fine but trying to pretend you do while comparing K10 to Prescott is a dead giveaway.

yomamafor2 said...

It is very likely that the 1.6Ghz Barcelona was cherry picked by AMD for Computex.

Charlie
The ones floating at the show are so broken they are not worth benchmarking. They are stable enough to finish up platforms and BIOSes, which is what this round of samples was meant to do.

They are far from full clocked, half the FP/SSE resources are broken, and the memory controller is barely functional.

On the up side, when they get debugged, things will get better/faster, presumably by a lot.

On the down side, they are not out, not imminent, and Intel has a new product coming out.

-Charlie


Although not posted on theInq, this was posted on a forum in realworldtech.

If Charlie really said so, then it might be true that the highest Barcelona can clock with current stepping is 1.6Ghz.

Another problem is that, if this is true, then AMD has a long long way to go, before releasing the Barcelona. You can forget about volume at the moment.

enumae said...

Abinstein
At dual-socket, the K8 system will lose to a Core 2 counterpart a bit in integer, but win a bit in floating-point;

Does this take into account Intel's capability to use Quad Core in 2P against AMD's Dual Core 2P?

Shouldn't price/performance be a major part of the purchase decision?

A simple SPEC search shows an AMD 4P 8222 (32GB RAM) scores 108 in SPECint, Intel's 2P 5355 (16GB RAM) scores 91.

If you had to buy this system, can you justify an 18% advantage for 3.5x ($8596/$2408) the cost just for the processors and 2x the cost of RAM ($2544/$1272)?

Obviously Floating Point is another story and a place where AMD's platform shines, but an AMD 4P 8222 (32GB RAM) scores 98.7, Intel 2P 5355 (16GB RAM) scores 60.9, giving AMD a 62% advantage.

Does this justify a 3.5x ($8596/$2408) cost just for the processors and 2x ($2544/$1272) the cost of RAM?

------------------------------

To point out, Intel 2P 5355 (16GB) compared to an AMD 2P 2222 (8GB) has an 16% advantage in SPECfp, and a 61% advantage in SPECint, but at a price.

The cost for the performance is 1.4x ($2408/$1746) just for the processors, and 2x ($1272/$640) for the ram.

------------------------------

Could you conclude from this that the price/performance leader is currently Intel?

Thanks.

------------------------------

(prices compared are Newegg Prices for Intel's 5355 and RAM for both systems, while AMD's 8222 prices are from AMD's June 5th price list)

bk said...

enumae

Why haven't you brought up the economics of AMD on the desktop where currently Intel has a performance advantage at the high end?

I know you try to come off as unbiased, but only bringing up these arguments to favor Intel shows your true colors.

Heat said...

If you believe:

1.) That AMD is lying even though this would be grounds for stock fraud and could get AMD upper management put in prison as well as fined.

2.)That every pro-Intel rumor is true while every pro-AMD rumor is false.

3.) That the Intel Compiler produces good code for K8.

4.) That the architectural changes to K10 compare at all to the handful of changes to Prescott.

5.) That a 1.6Ghz system was the fastest cherry picked chip that AMD could scrape up for Computex.

Then that goes a long way to explain your point of view.

If you don't understand cpu architecture that is fine but trying to pretend you do while comparing K10 to Prescott is a dead giveaway.


Thanks for deleting my post very classy.....

If you believe:

1) That AMD has a 2.4ghz chip while they demo a 1.6ghz chip all over.

2) That their partners are lying when they say they have not been able to clock those chips more than 2.0 and even then they can only manage it to barely run.

3) AMD's lack of info is based on their tight security rather than a dud chip..

4) C2D is only winning because of benchmark optimizations...

5)That there are actually pro Barcelona reliable third party rumours other than what AMD shows on their slideshows and made up screenshots by the INQ and FUDzilla...

Then that goes a long way to explain your point of view.

If you don't understand the common sense of business practices that is fine but trying to pretend that most of the speculations that you talk about will somehow change AMD's current predicament is a dead giveaway......

enumae said...

BK
...I know you try to come off as unbiased, but only bringing up these arguments to favor Intel shows your true colors.

Wow! I ask a few questions to Abinstein, you don't like what I have shown, and now I am showing my true colors...lmao, what a joke.

I enjoy debate about the topics at hand.

Do I have brand preference, yes, I use Intel, does that negate the points/questions I brought up to Abinstein?

Did I lie or make false claims?

Did you just not like my post?

-----------------------------

As to your other comment, I went ahead and prepared some numbers, but it wouldn't apply to the context of which my post was about... Price/performance for 2P and 4P servers.

abinstein said...

enumae -

"Does this take into account Intel's capability to use Quad Core in 2P against AMD's Dual Core 2P?

Shouldn't price/performance be a major part of the purchase decision?"



I am comparing only the dual-core versions of K8 and Core 2. With Core 2 Quad, Intel is indeed at a price-performance advantage against dual-core K8. This is why AMD is losing server sales.

However, for the long term, Opteron systems are IMO more cost-effective than Core 2 counterparts. A 2-socket dual-core Opteron bought early 2006 can upgrade to quad-core and enjoy mid-to-high level (relatively speaking) performance till late 2008 and further. This is 3+ years of scalability to best-in-class performance.

OTOH, a 2-socket quad-core Xeon bought in late 2006 will be out-run by a similar quad-core Opteron a year later, and has no further upgradability what-so-ever. I reckon though most system buyers screw themselves by not thinking in the long term.

abinstein said...

Heat -
"Higher performance products.....not according to scientia and abinstein...."

I don't think you understand. Higher performance products means systems with 8 cores or higher. Of course AMD is losing it because Intel's 8-core systems are much cheaper than AMD's.

Mr. Richard is right about 50% benchmark wins, too, if you look at SPECint and SPECfp. He actually is reckoning the same thing as I did on my (earlier) blog articles. What he didn't mention is that K8 wins a bit more benchmarks in SPECfp, and lose a bit more in SPECint. Sales demanding integer performance however is quite higher than those floating-point. That is why some buyers have been switching.

BTW, the site is clearly manipulating the words spoken by Richard. Everything it quotes speaks in past (perfect) tense. However, everything it concludes is in present/progressive tense. It's probably hoping to sway the stock market to its liking by taking advantage of the responses from English reading-challenged investors.

Scientia from AMDZone said...

heat

Stop making up my position. I get really, really tired of correcting your misrepresentations. You don't need to try to prove that C2D is faster than K8 because that is not an issue. It is only in your imagination that you think I that believe otherwise.

There is no doubt that C2D is much, much faster than K8 in SSE. The only real question is just how much faster it would be in Integer if the benchmarks were all compiled with PGI. The rough suggestion is that C2D's lead in Integer would drop to 10%. However, without real benchmarking it is difficult to tell. Okay, now each of your points:

"1) That AMD has a 2.4ghz chip while they demo a 1.6ghz chip all over."

Yomamafor2 apparently has the same misconception. Please get your facts straight though. The 1.6Ghz system was not demoed by AMD. This was a vendor system who had received an ES chip from AMD. This system in no way reflects the current status of K10.

If you were more observant you would wonder why they didn't mention the vendor by name. For example, if this vendor were, say, HP or nVidia then this would add a lot of weight to their argument that K10 is in bad shape. They didn't mention the vendor by name because that vendor only rated an ES chip and they don't want the facts to get in the way of some good FUD.

"2) That their partners are lying when they say they have not been able to clock those chips more than 2.0 and even then they can only manage it to barely run."

And, those statements are perfectly consistent with ES chips. You don't seem to understand how the sample process works. The vast majority of small vendors get chips solely for electrical verification. The chips only need to be able to boot, not run with blazing speed. This chips are typically running with lots of BIOS patches. I guarantee that you have not heard from anyone who requires a properly working chip for development.

Again, if you can name these partners then that could add weight to this claim.

"3) AMD's lack of info is based on their tight security rather than a dud chip."

Again, if you don't understand cpu architecture that is fine.

"4) C2D is only winning because of benchmark optimizations..."

This is your strawman argument. C2D would still blow K8 away in SSE and would still win in Integer even with PGI. However, proper PGI compiling could perhaps cut C2D's Integer lead in half.

"5)That there are actually pro Barcelona reliable third party rumours other than what AMD shows on their slideshows and made up screenshots by the INQ and FUDzilla..."

But according to you if it doesn't favor Intel then it isn't reliable, right?

Ho Ho said...

abinstein
"A 2-socket dual-core Opteron bought early 2006 can upgrade to quad-core and enjoy mid-to-high level (relatively speaking) performance till late 2008 and further"

Interesting, I always thought that DDR2 K8 was released in August 2006, not early 2006. It was just a bit after Core2. Depending on definition of "early 2006" that can make a difference of more than half a year.


scientia
"They didn't mention the vendor by name because that vendor only rated an ES chip and they don't want the facts to get in the way of some good FUD."

Of cource that secrecy couldn't be because of the tight security surrounding Barcelona wouldn't it? What would have happened to that vendor if it would have publicly stated that the Barcelona they have sucks?

Another interesting thing is that in that story about 1.6GHz being the best thing they have they called it latest revision currently availiable. You said it was at least two revisions old. I don't remember you telling on what information did you base that idea.
Yet another interesting thing is that ES of Core2's were one of the best overclockers. Often a lot better than retail ones.


"C2D would still blow K8 away in SSE and would still win in Integer even with PGI. However, proper PGI compiling could perhaps cut C2D's Integer lead in half."

I'd be really interested to hear what compiler is used to compile most of the software. My educated but unverified guess would be MSVC, a compiler that has by far the worst optimizer of all the better known ones (GCC, ICC, PGI). From what I know it shouldn't be favoring one CPU to another, unless you consider that MS chose AMD64 as their base CPU for developing Windows 64bit edition and they chose to do something about that.

Aguia said...

Yet another interesting thing is that ES of Core2's were one of the best overclockers. Often a lot better than retail ones.

That’s because they aren’t Intel so they do things differently?
While Intel wants to show you how good their new chips are even if it’s just their own chips, not yours, is good?
Maybe good marketing ...

In some sort a lie is better than the truth is that what you mean?

Aguia said...

Even if AMD quad does show up at 1.6Ghz.
We still win, Intel will have to lower their prices and AMD will give us very cheap quad core processors (if they perform bad [and/or clock low]).

Good times for me, cheap systems. No longer mater who is the best.
If it’s not an Intel Pentium 4, Pentium D or a Celeron then it’s a good processor!

Ho Ho said...

aguia
"That’s because they aren’t Intel so they do things differently?"

I only said that it was interesting, nothing more. Not always are the ES CPUs much worse than retail ones.


"Intel will have to lower their prices and AMD will give us very cheap quad core processors"

Well, Intel has planned their price drops nearly half a year in advance. I remember hearing about Q2 and Q3 drops in late December. After 22'th July you can get 2.4GHz Q6600 for $266. What do you think how much will comparable AMD cost?

Aguia said...

What do you think how much will comparable AMD cost?

Like I have already said I think if it really performs worst than Intel current offering it will be priced lower, if not we will still have the Intel price drop, so very good for us.

This time there aren’t bad processors to buy.
Not having the chance like in the past to buy the X2 and have to go for the much worst offering like the Pentium D.
This will not happen this time, when going for AMD or Intel.

Even if the AMD will be much better do you consider a cheaper E6320, E6420 a bad buy? Or the Q6600 a bad processor (bad buy) even if the AMD lower performing offerings surpasses it in 10% 20%?

Ho Ho said...

aguia
"Like I have already said I think if it really performs worst than Intel current offering it will be priced lower"

That would certainly be logical in most cases. Though Barcelona won't have too good availiability at start so things might not be that logical. I think we might be able to make better estimates after 22'th July price drop kicks in.


" if not we will still have the Intel price drop, so very good for us."

No question about that. I too enjoy those awfully low prices. Only thing I'm afraid of is AMD getting (financially) beaten too hard so Intel would once again dominate the market and dictate prices as it sees fit.


"Even if the AMD will be much better do you consider a cheaper E6320, E6420 a bad buy?"

Of cource not. I'm simply rather sceptical about AMD having low prices on their CPUs. I'm sceptical because as AMD won't be able to generate much revenue from Barcelona at first those won't be cheap CPUs. In August AMD's fastest K8 will be competing with CPUs in $166-$183 price range. They will be having hard times ahead, there is no question about it.


"Or the Q6600 a bad processor (bad buy) even if the AMD lower performing offerings surpasses it in 10% 20%?"

I'm not sure what you mean here. Was it meant to be "lower costing"?

Anyway, I personally don't care much about what company CPU I am using, I only care how much it costs me to get one of those. Or in other words, I choose CPUs by their bang for buck ratio.

Though as I currently already have s775 system it would be a bit more expensive for me to make a platform change. If Barcelona would be either considerably faster or considerably cheaper I will most definitely think about it.

I'm very interested in how will V8 vs 4x4 end up. I could surely use all the performance they would give me. Currently AMD charges massive premium for their 4x4 CPUs and I know next to nothing about Intel.


Yet another plus for Intel might be that its future chipsets will have support for both SLI and CF. If I remember correctly then support for both will be already there in X38. Though for me personally that doesn't matter, I probably won't use the power of even single midrange GPU :)

Aguia said...

Yet another plus for Intel might be that its future chipsets will have support for both SLI and CF. If I remember correctly then support for both will be already there in X38. Though for me personally that doesn't matter, I probably won't use the power of even single midrange GPU :)

That’s an area that I have been looking too.

140$ mobo + 140$ GPU1 + 140$ GPU2
2 x 7900gs or 2 x 1950gt/pro?

It’s hard because I have to change the mobo just because of the GPU.
If that really comes out Intel will have an Ace in the high end.

bk said...

enumae
Do I have brand preference, yes, I use Intel, does that negate the points/questions I brought up to Abinstein?

I have not seen you state your Intel preference before. If I have missed that, I apologize. My comments where based on the perception that your past comments about AMD vs. Intel are unbiased. You have accused Scientia of being an AMD fan, while you portrayed yourself as in the middle.

I have nothing against what you are saying. I just like to know which side of the fence someone stands. It is probably obvious that I stand on the AMD side.

To your credit I don’t think you twist and exaggerate the facts like some others do. Those that do that are easy to distinguish.

abinstein said...

Ho Ho -

"I always thought that DDR2 K8 was released in August 2006, not early 2006. It was just a bit after Core2."

You're right; it's about a month later than Core 2 Quad. Thus Core 2 has a clear lead on high-performance servers for the same number of sockets for about a year. The release of Core 2 Quad makes the only interesting K8 system to purchase during this year the 4-socket ones. It's thus not difficult to imagine -
1) Why AMD's losing server market share
2) Why AMD would release server Barcelona first

enumae said...

BK
You have accused Scientia of being an AMD fan, while you portrayed yourself as in the middle.

I believe I had accused Scientia of being an AMD hopeful, I do not recall calling him and AMD fan.

Still, if I had, it would have been meant more along the lines of my definition of AMD hopeful (from a few topics ago) which is a person with brand loyalty.

Scientia roots for AMD, while I root for Intel. I do not want AMD to fail, nor do I feel Scientia wants Intel to.

I believe what we both want is for both companies to make there best products, and then see how there best products compare against each other.

----------------------------

I try and keep my brand loyalty separate from my opinions. I try and base post I make on facts or linkable sources.

If we start talking about future products, that is where my Intel hopeful side could/would show, as is I believe is the case with Scientia.

Scientia from AMDZone said...

ho ho

""Interesting, I always thought that DDR2 K8 was released in August 2006, not early 2006."

Sorry ho ho. AMD released the Orleans and Windsor cores (revision E, socket AM2) May 23, 2006. Early is correct.

"It was just a bit after Core2."

Well, actually you are right. Conroe was first reviewed in March 2006 so AM2 was about two months later. My guess is you are confusing the first reviews with the actual launch of Conroe which happened six months later.

"Of cource that secrecy couldn't be because of the tight security surrounding Barcelona wouldn't it?"

The way the process works is that compiler writers get priority because they have to include the new capabilities. So, PGI, Novell, Sun, IBM, and Microsoft would get preference. They would need fully functional (although probably not full speed chips) as soon as possible. Then as each revision improves they would get first updates. Companies working on virtualization and possibly some designers working on hand coded drivers (nVidia, VIA, etc.) might also get preference. I don't think Cray makes its own compiler so it might not be preferred. Most vendors and partners get barely functional ES chips.

This is not due to NDA because it is simply not credible that top designers at any large company would be chatting up web journalists. The people they get access to are down the foodchain a few levels and therefore are not aware of K10's current status.

"Another interesting thing is that in that story about 1.6GHz being the best thing they have they called it latest revision currently availiable."

It could very well be the best chip they could get. Non-preferred vendors do not get regular ES updates. For example, if you are building motherboards then you get an early sample for electrical verification and then a later update to confirm BIOS function. BIOS is lower priority since it can be readily changed even a couple of weeks before launch while motherboard design cannot be.

"Yet another interesting thing is that ES of Core2's were one of the best overclockers. Often a lot better than retail ones."

Well, not quite. The first ES C2D chips available were stepping A1 and the best of these topped out at 2.4Ghz. The B0 stepping topped out at 2.66Ghz while B1 would reach 2.93Ghz. The actual launch chips were revision B2. There was some discrepency where the B1 chips seemed to overclock better than the B2. However, the earlier A1 and B0 chips did not overclock as well.

At any rate, Intel did improve the clock roughly 500Mhz as the process improved with each stepping. We can still see this with quad cores now reaching 3.0Ghz while they were previously at 2.66Ghz.

It would be no surprise to me at all if early ES chips only clocked to 1.6Ghz and later ES chips clocked to 1.8 or 2.0. Supposedly, these are B0 and B1 chips while current chips are B2 with B3 being the actual release stepping.

"My educated but unverified guess would be MSVC"

I agree. There shouldn't be any preference with MSVC or GCC. However, few game designers use MSVC and I know some graphics software like Photoshop uses ICC.

Ho Ho said...

scientia
"Sorry ho ho. AMD released the Orleans and Windsor cores (revision E, socket AM2) May 23, 2006."

I think you missed the part I was quoting, we were talking about Opterons, not desktop CPUs.
AMD press release


"Early is correct."

So your definition of "early" is mid-Q2. Wouldn't that make mid-Q3 late 2006? Kind of loose definitions in my oppinion, especially considering you can't fit mid-year anywhere with such time frames.


"However, few game designers use MSVC and I know some graphics software like Photoshop uses ICC."

Do you know of a way how to recognize what CPU was used to compile a certain binary? It would be rather interesting to make some statistics.

Also I highly doubt game developers use ICC without doing something about its multipath things. They must be using something like this so their games would run decently on non-Intel CPUs also. After all just a year ago one might have said that most gamers used AMD CPUs. I know that was so in Estonian PC enthusiasts forum.

Scientia from AMDZone said...

It took me a bit to sift through the bad Cinebench Barcelona scores plus FX-74, Xeon 5365 and Penryn.

My best estimate is that Barcelona will only lead Penryn by 5% at the same clock on Cinebench.

Pov-Ray is a bit tougher to tell but it looks like AMD would at best match Penryn or may be slightly slower.

The claims of Penryn's being twice as fast or 30-40% faster than Barcelona are fantasy. However, I can understand why someone would think this based on the scores.

Ho Ho said...

Considering that Intel has said that Penryn will be 40% faster than Clovertown in SpecINT_rate and if Barcelona won't be considerably faster than Clowertown then it might be true that Penryn is 30-40% faster than Barcelona in that benchmark.

Of cource we don't yet know how much of that speed increase is from higher CPU and FSB frequency.


Btw, did you compare Barcelona vs Penryn at same frequencies in those benchmarks?

Scientia from AMDZone said...

ho ho

The dropoff on Clovertown is about 25%. And, Penryn seems to be about 9% faster. So, if we remove the dropoff and add the 9% gain that would be 145%. So, a 40% gain seems reasonable.

With Barcelona we have a claimed 20% increase over Clovertown. However, this isn't a real figure as it is simply K8 X 2. A 20% increase in speed over K8 puts us at 144%. So, K10 and Penryn should end up with similar speeds at the same clock.

To get the suggested Pov-Ray and Cinebench scores, Barcelona's hardware would have to have a major flaw which prevented any gains from the numerous improvements. However, if this were the case, AMD would have to go ahead and release K10 and work on another revision much as Intel did with Williamette. Since they haven't done this it is much more likely that the scores were done on earlier steppings that required BIOS patches. These could easily eat up any performance gains. The last number suggested was that the release would be B3 whereas Intel released at B2. Again, this seems consistent with what we've seen.

The only other alternative and apparently the one that Intel fans believe is that AMD has not one but two problems with K10. That would be both a hardware flaw that reqires another revision plus problems with the steppings. By this theory, when AMD does finally release K10 it still will not show any large gains.

So, those are the two possibilities. I think the BIOS patch is more likely but it is possible that AMD has a major flaw with K10 that cannot be fixed this year. I assume AMD will be more talkative at the meeting at the end of July.

Axel said...

Scientia

AMD has K10 quad currently clocking to 2.4Ghz without any trouble.

I've noticed that you continue to make categorical assertions without http links. I'm sorry but your assertions have little value or credibility without these links (and no, Fudzilla & Inquirer links don't count). So please provide a link to evidence that AMD is clocking K10 to 2.4 GHz without issue. I (and most of the folks reading this blog) simply believe very little of what you write without evidence. Your track record of predictions over the last eight months has not helped your credibility.

Again, LINKS PLEASE.

lex said...

Some random musings..

Its most interesting how we are at the crest of "summer" and we hear not a single substantiated rumor of healthy parts. For AMD and for the AMD rooters this is the single most important event. Never has there company been so on the ropes. I find it impossible that in dealing with the multitude of suppliers that Barcelona is anywhere near prime time. That in my mind says it all. THey are most likely on their second or third full design spin with a few metal spins as well. To not be near healthy for stability or speed tells you all.

For AMD time is of essence. If they don't get this product released and can't get the attention shifted to how far superior they are to C2D on a apple to apple process node the impact of coming after Penrym will be muted.

I got to believe there is a lot of tension in Dresden these days. What could be worst? Filling your factory with money losing K8s and spinning your wheels pushing new steppings only to hear nothing but bad news back...

Fujiyama said...

I have to agree that nobody knows the truth about Barcelona. It can be faster, it can slower than Penryn or even Clovertown.
K10 is a proof that large projects are disaster and the way AMD took this way is similar to Windows Vista.
Big announcements, simulations and then very little impact on user experience.

Maybe it is not too late (but it is) to get K8 attach large L3 cache and produce MCM quad core with separate L3 for each dual-core inside. AMD should do it a year ago instead of Brisbane or just make another revision to this core.
Than make another revision and another with smaller steps seen from user perspective (in a shop).

K10 is also a proof than AMD has a weak, weak management because observed time-to-market and competitive position for last 10 months is the worst I've seen ever.
Except price slash AMD did nothing to change the market situation.
They are just waiting for K10, betting on one project.
We hear about Torrenza, Raiden, Trinity, DTX, new chipsets and graphics but none of this except R600 is a product. They are only promises for the bright future.

T800 said...

I keep hearing the theory that AMD cannot tip their hand and show early hardware and benches due to various reasons.

But I think it has gotten to the point where the longer AMD takes to bring out Barcelona for real, the worse the actual product launch will be. Why? Because the longer it takes, the more anticipation is built up, and AMD's image continues to take a beating. Inevitably, the longer the delay the more people are going to expect of AMD when Barcelona does launch.

Essentially AMD will never be able to live up to the anticipation, and any launch short of a spectacular extravaganza may end up being perceived as a failure.

Will this actually happen? Perhaps not, but it holds just as much water as the theory that AMD will only stand to hurt themselves by showing early hardware and benches.

I've said it before and I'll say it again. AMD needs to give the world a hard launch date for K10. Not an announcement in 2 months, not vague Q3 ship promises, an actual launch date. I don't know about anyone else, but this is the only thing that will restore some of my confidence back in AMD.

gdp77 said...

t800 I don't agree. The more they delay to release Barcelona, the more people understand that they have problems and it will finally be a mediocre cpu. Intel demoed penryns @ 3.33 GHz and people could play with them... AMD showed closed cases and people couldn't even touch them. Believe me, this leads to the conclusion that barcelona is not what we expect. Barcelona will be marginally better than today's conroes and will eat penryn's dust...

U will see I am right.

Aguia said...

axel,

some link:
Final AMD "Stars" Models Unveiled

AMD Phenom Models

lex said...

Why AMD is not tipping its hand

1) THeir current Barcelona stepping is full of issues. Either too slow, too buggy and unstable. And showing it woul reveal to the world how pitfully slow it is.

2) It is overal very healthy but well isn't stellar. I guess that is still case 1).

3) It is stellar. They want everyone to count them out. They want their customers to be in the dark. They want to catch INTEL sleeping. Slow to push Penrym, slow to ramp their 45nm factories.. IE to give up.
How likely is that... ?

I guess all of AMD's hope must be on that stepping revision running thru the factory and management is praying that the designers actually got a handle on the big bug. The question is did they have the balls to convert all of their silicon to the new stepping before they see it.

That is the only reason they 3rd quarter launch date is so vague. The simple fact of the matter at this moment AMD still doesn't have fixed and healthy silicon in their hands. Sure this next stepping may fix everything.

You guys figure the odds. AMD is ramping a completely new 300mm factory, new IBM invented 65nm technology. Recall IBM is no powerhouse in manufacturing hundreds of millions of high performance cpus. THey are trying to debug and get a highly complext new architecture done. And the whole company is bleeding red ink.

You'd think under those conditions if they knew exactly when this launch was going to happen they'd tell you.. They can work out the fab time to a couple days, assembly time to a couple days, test time to a couple days. If thie silicon was in hand and healthy they'd tell you the launch date. NO launch date means NO healthy silicon.

Too bad AMD

Axel said...

Aguia

some link:

I appreciate the effort but those are only links to AMD's roadmap and expected launch frequencies. I'm not looking for any words from AMD, we already know they have lied in the past. Remember just recently:
- "R600 will be launched top to bottom in May."
- "We don't do soft launches."
- A month later, R600 paper launched except for the HD2900XT.

So nothing from AMD please, I don't believe them. I'm looking for a link from a trusted source to provide evidence supporting Scientia's assertion that "AMD has K10 quad currently clocking to 2.4Ghz without any trouble."

abinstein said...

"- "R600 will be launched top to bottom in May."
- "We don't do soft launches."
- A month later, R600 paper launched except for the HD2900XT."


I remember AMD said the top to bottom launch is by the end of June.

abinstein said...

"Barcelona will be marginally better than today's conroes and will eat penryn's dust..."

If K10 is marginally better than Conroe, then Penryn will at the best be marginally better than K10.

Ho Ho said...

abinstein
"I remember AMD said the top to bottom launch is by the end of June."

When did it say so?

I remember this:
"AMD has confirmed that R600 will be delayed yet once more. The Direct3D 10 hardware was first slated for late November or December for the holiday spending season. That date was moved to January then February and then we were told the specifications and architectural details would be made available in March. This was to coincide with CeBit in Hannover, Germany. Product was then earmarked to ship in late March."

Axel said...

abinstein

I remember AMD said the top to bottom launch is by the end of June.

You're falling into the same trap as Scientia: expecting us to believe your statement at face value without a link. Please provide links next time if you remember AMD saying something.

Here's a link showing that AMD said in early April that they would do a one time launch of the entire family of DX10 enabled products:
http://www.xbitlabs.com/news/video/display/20070403235139.html

And then two weeks later during the Q1 CC, AMD claimed they "do not do soft launches."
http://seekingalpha.com/article/32901

So please always support your statements with links, otherwise you're wasting your keystrokes on an audience that is ignoring you.

lex said...

If K10 is marginally better than Conroe, then Penryn will at the best be marginally better than K10.

If this happens then AMD is finished as Penryn is far cheaper to manufacturing as a 2x2 then native quad and smaller too. AMD can't hope to compete on performance and thus will be relegated to the under 1K computers and have a ASP of less then 100 bucks. Can you say BK in 2008?

Joshua said...

We need to take a look back in history. AMD has always kept quiet about their designs so K10 might be what C2D was to athlon 64. But R600, ehhh...... well it's no good for high end gaming. They even said they aren't releasing it yet so that way they can buy time and fix the design.

abinstein said...

"If this happens then AMD is finished as Penryn is far cheaper to manufacturing as a 2x2 then native quad and smaller too."

I believe you are very wrong. While it's quite long and painful to explain this in the comment area, please read my blog article instead.

abinstein said...

axel -
"Here's a link showing that AMD said in early April that they would do a one time launch of the entire family of DX10 enabled products:
http://www.xbitlabs.com/news/video/display/20070403235139.html"


You fall into the same trap as Ho Ho, that you start calling others liars without proof. The link you showed actually says a top-to-bottom launch in the 2nd quarter, which hasn't ended yet. In fact, EE times reported in Feb 2007 that R600 top-to-bottom release would be "by the end of June." (I also recall a Hector or Henry interview speaking of the same thing, but can't find it now.)

In any rate, I'll most believe that ATi had R600 in bad shape when AMD acquired it, and that was reflected in the first delay from December '06 to March '07. Then AMD delayed it again from March to June, probably because the resulting high-end parts from the 1st run are not great enough in quantity for a real launch.

In an interview in late 2006 (or a conference call, I forgot), Henry Richard says AMD still plans to launch R600 in March (1Q 2007). He was being frankly conservative, just short of offering the exact numbers. The reason behind his conservation is not difficult to see: he didn't know whether enough number of high-end parts will come out of the 1st run. It turns out the volume is not large enough, and AMD decides not to make a paper launch in March, but in June.

abinstein said...

By the way, axel, feel free to ignore me. I can care no less. In any rate, your claims of AMD lied are pure lies themselves, and you only prove yourself a liar:

- In public, AMD planned to release R600 in March, but then delayed it to June for a top-to-bottom launch.

- AMD is not soft-launching anything as long as it ships R600 variants by the end of this month (which it does).

- AFAIK, AMD has never said anything publicly about launching R600 in May (your claim).

Just ignore me, as you've always did. But be sure that if you lie, I will not ignore to correct you.

abinstein said...

Oops... a small correction to the end of my 2nd previous comment, which should read as this:

"... and AMD decides not to make a paper launch in March, but an actual launch in June."

Thanks.

Axel said...

abinstein

AMD is not soft-launching anything as long as it ships R600 variants by the end of this month (which it does).

No. It's really very simple to see the lie:

- AMD "launched" the entire R600 series in May. See:
http://biz.yahoo.com/bw/070514/20070513005059.html?.v=1

Here's the money quote from that press release:

"AMD (NYSE: AMD - News) today introduced the ATI Radeon HD(TM) 2000 series, a top-to-bottom line of ten discrete graphics processors (GPUs) for both desktop and mobile platforms."

- However, availability of the mid-range cards is expected in June. From the same link, "The ATI Radeon HD 2600 and ATI Radeon HD 2400 cards is scheduled to ship in late June with pricing to be announced."

- That is the definition of a paper launch, or "soft launch".

- Hence Henri is caught in a bald-faced lie when he said in the Q1 CC, "We do not do soft launches."

If even now you're too stubborn to admit you're wrong, it just means you've got the head in the sand. I'm sorry but AMD is in for a world of hurt over the next year as Barcelona is suffering major yield & speed issues. What's hit them so far financially is only the beginning, the Intel steamroller hasn't even arrived yet.

gdp77 said...

If this happens then AMD is finished as Penryn is far cheaper to manufacturing as a 2x2 then native quad and smaller too. AMD can't hope to compete on performance and thus will be relegated to the under 1K computers and have a ASP of less then 100 bucks. Can you say BK in 2008?

I have many times expressed my opinion that AMD will go BK in Q1 08, unless barcelona performs miraculously well (which i don't bealieve that will happen). Since scientia has written many posts for the future i would like to see a post like "what the computer world will look like if AMD go BK in 6-10 months.

abinstein said...

"That is the definition of a paper launch, or "soft launch"."

What I see unfortunately is your lack of understanding the plain English. The press release is by no mean contradictory to AMD's previous position, that a top-to-bottom range of products will be made available by the end of June.


"I'm sorry but AMD is in for a world of hurt over the next year as Barcelona is suffering major yield & speed issues."

I'm sorry, too, not because I care for AMD, but because a world lack of AMD will be harsher for all PC buyers. Over the past 10 years or so, the company has been instrumental in bringing the x86 computing forward. Intel OTOH did virtually nothing instead of making failed Itanium and Netburst, except the highly & successfully tweaked Core 2.

I have literally no idea why whenever I speak of AMD in the technical terms, there are people (probably Intel investors, Intel employees, or stock traders shorting AMD, I don't know/care) coming up with arguments on AMD's financial situation. It is plain simple to see the reason why AMD decided to delay top-to-bottom release of R600 to June; then it is plain simple again to see why AMD decided to release the high-end part a bit earlier (in May). Let me reiterate the plain simple reasons again -

1. In March, AMD didn't get enough high-end parts in March, thus wasn't able to make a full/real launch until much later.

2. In April/May, the chips returning from the foundry probably perform better, and thus an earlier high-end launch was possible.

If the 2nd point above happens to your company, would you stick with your old plan to release the highly-anticipated product by end of June, or to release it as soon as possible? This is really a no-brainer. In any rate, a top-to-bottom launch in Q2 is not a lie when Q2 is not yet past. Just because a company is in bad financial term doesn't make its executives a liar, but those who think so absolute FUDers.

As for Barcelona's problems and delays, again, summer is not here/over yet. The only thing I'd care, being a professional engineer/scientist, is whether my computing need can be doubled with cheap cost and the same TDP by the end of this year. Spreading AMD's financial or bankruptcy FUDs won't affect a bit of my wait, except making you look stupid.

Ho Ho said...

abinsein
"It is plain simple to see the reason why AMD decided to delay top-to-bottom release of R600 to June; then it is plain simple again to see why AMD decided to release the high-end part a bit earlier"

I wonder if similar thing could be applied to Barcelona ...

Axel said...

abinstein

The press release is by no mean contradictory to AMD's previous position, that a top-to-bottom range of products will be made available by the end of June.

You're still not getting it. Refer again to my quote from the May 14 press release, this time with boldface emphasis on the key words:

"AMD (NYSE: AMD - News) today introduced the ATI Radeon HD(TM) 2000 series, a top-to-bottom line of ten discrete graphics processors (GPUs) for both desktop and mobile platforms."

What about "today introduced" do you not understand? On May 14, AMD launched the entire R600 series of GPUs. However, only the HD2900XT would be immediately available. Everything else is paper launched or soft launched with availability later in the year, supposedly June. Hence Mr. Richard lied, plain and simple. One month before launch it's a certainty that he knew about the R600 problems and lied through his teeth during the CC.

If you still don't get it, it's going to take something more serious to get you to throw out those rose colored glasses. No availability of Barcelona in 2007 should do it.

abinstein said...

axel -
"What about "today introduced" do you not understand?"

I'm sorry you have poor understanding of plain English. The statement you quoted is just the summary of the following:

* Today AMD introduces HD 2000 series.
* HD 2000 consists of a range of products from top to bottom.
* Initially only 2900XT will be available.

Thus what is launched or released is only 2900XT, but not others.

You can keep your own way of defining soft-release. But the fact that 2Q is not over yet, and a top-to-bottom range of R600 cards will be available by its end, proves AMD was not lying before or after the press release.

Scientia from AMDZone said...

I thought about commenting but there are too many issues. So, I'll have to do another article.

BTW, the employees from Intel have been particularly curious lately. They have topped every other single source with 500 visits in the last month.

The question of whether AMD is just keeping quiet or hiding problems is reasonable. I'll see if I can address this in my article.

abinstein said...

"BTW, the employees from Intel have been particularly curious lately. They have topped every other single source with 500 visits in the last month."

Hi Scientia, I have a (possibly very dumb) question - how do you know where a view on your blogspot article is from? Thanks!

Ho Ho said...

According to the HTML source he is using Google analytics and statcounter.

I personally have only used Google analytics and it is rather nice. Among lots of othed data it is able to show from where traffic is originating.

Dr. Yield, PhD, MBA said...

BTW, the employees from Intel have been particularly curious lately. They have topped every other single source with 500 visits in the last month.

500 visits out of 90k employees? I would venture to guess that The Onion gets that many hits in the first half of a Monday morning. ;)

Seriously, back in the day I worked in the chip end of the business, I read rumor mill blogs/pages as much for entertainment as anything else.

Scientia from AMDZone said...

Yes, Ho Ho is right. I look at the Analytics reports. The reason I can tell Intel is because they have their own domain.

Dr. Yield, normally I wouldn't consider Intel that significant but it is much higher than others. For example, I don't get anymore AMD traffic than I do from places like Boeing or HP. This is about what you would expect from casual readers. However, Intel traffic is about 100X higher with less than 10X as many employees as AMD.

I was told by Jeff (whose link at Intel is on my home page) that he emailed my blog address around to the technical staff. I did checks on this one time and found out that it wasn't just one Intel location. I get Intel traffic from most of their sites. I don't know if they find it hilarious, irritating, or just moderately interesting but they are apparently still visiting.