How We Got Here -- The X86 Industry In Perspective

In my last two articles I argued both sides of the Intel/AMD aisle to get a measure of the people who comment. With that perspective in hand it's time to get back to real posting. I'm going to look in detail at X86 development over the past twenty years to see how we got here and where we can go.

AMD has a very noticeable four year develop cycle. AMD released the RISC 29050 processor in 1990. AMD then reorganized the RISC team and started working on a new X86 processor. It appears that mostly what AMD did was take the 29050, strip down the register set, and put a micro-code X86 instruction translator on the front end. This effort took five years and the K5 was released in 1995. The performance was not spectacular but for AMD's first completely new X86 design it was a reasonable result. In fact, the K5's biggest problem was not its performance but its inability to achieve higher clock rates. This appears to be more related to process technology than chip architecture. Four years later in 1999 the K7 was released and four years after that in 2003, the K8 was launched. We are now looking at the K10 four years after K8. Clearly, this is a four year development cycle. K6 is an exception in 1997 but that was because it was created by the separate Nexgen design team. The pattern since K5 is a four year major architecture cycle with a smaller team doing updates in between.

It only took Intel three years to get from 80386 to 80486 but the bar since then has also been four years. It was four years from 80486 in 1989 to Pentium in 1993. However, the extraordinary thing about Intel is that it was running not one but three separate microprocessor design teams. The second team was working on the iAXP432/i960 line and the third team was working on the VLIW i860. There is no doubt that the i860 team was put on Itanium development. Presumably, the i960 RISC team was reassembled into the Pentium Pro team. We know that Pentium Pro had a RISC core and the development would have had to start in 1991 which was during the time that Pentium was still under development. The four year pattern at Intel picks up again with Williamette. It is four years from Williamette in late 1999 to Prescott in late 2003 but then five years to Nehalem in late 2008.

Williamette was an exception in that it appeared five years after Pentium Pro but, curiously, it wasn't really complete. Williamette's performance suggests that it was rushed, yet there should have been more than ample time in the five years to get the design right. Since Northwood was a good design we can probably work backwards four years to late 1997 which is fully two years after Pentium Pro was finished. The best guess is that Intel expected Itanium to take over the top end on the desktop. When they realized in 1997 that Itanium was going to be late they hastily assembled the Williamette team and rushed it out. Since Northwood's launch probably coincided with the 130nm process it is probable that the Williamette team was assembled in early 1997 and that Intel decided to skip 180nm for Northwood. Northwood just two years after Williamette

The Williamette team went on to create the Northwood and Prescott designs but then presumably abandoned two years worth of work on Tejas in 2005. This cancellation would explain the extra year to Nehalem which presumably would have been 2007 if Tejas had not been canceled. I have a very strong suspicion though that any of the Tejas work that was useful was applied to Nehalem II. Obviously this wouldn't be the original Nehalem but this could indeed mean that C2D version of Nehalem could be more than just a two year refresh of the Conroe Design. Apparently, a third (or fourth) design team was assembled in Israel in 1999 to work on Timna which was a cost reduced version of PIII. This was a good design but was sunk by the onboard RDRAM controller in 2001. This team apparently then began working on Banias which was released in 2003 as Pentium M. Banias too has a look of being rushed. The most logical conclusion is that the Haifa team was able to use a lot of the Timna information to put together a reasonably good design. There is no doubt that Banias is an upgrade of PIII but it reached a better state of polish with Dothan.

However, Conroe is a mystery. The quality of the design suggests the same four year cycle but this would imply that work began on C2D in 2001 when Timna was canceled. I've seen some suggest that Conroe was an upgrade of Yonah but this is clearly not possible; the gap between Yonah and Conroe is far too large and the time between releases is far too short. I've seen others credit the Conroe design as a derivative of Banias but this too is suspect because both Williamette and Banias had deficiencies when rushed and nothing about the Conroe design stands out as a deficiency. There is however one clue in Intel's history that is peculiar. We know that Intel specifically avoided patenting all of the tricks that went into Banias. Looking back at this fact I'm skeptical that the successor to the mobile versions of PIII would cause this much concern for Intel. It is a certainty that Intel was aware of Prescott's problems by 2002. However, it seems more likely that after design work on Prescott had been going on for more than two years that Intel was having doubts in 2001 and that the work on Banias was folded into a larger design project including Conroe. We could assume that Intel realized the problem with Prescott in 2002 and was impressed with the completed Banias design and then began working on Conroe however this wouldn't seem to explain Intel's unusual move in hiding the patentable characteristics and, again, the Conroe design seems far too polished.

Since the separate Penium M line has now been abandoned in favor of the C2D Merom, we would seem to need one less design team. However, it is hard to believe that Intel which has always had three design teams is now down to just two: the Itanium and the C2D line. We either have to assume that the added items like CSI are taking an entire extra team and two teams are working on C2D or perhaps that the third team was put on special projects like the TeraFlop chip. I find it unlikely that Intel cut out the third team as a cost saving measure since dropping this many engineers would surely have been noticed. If the third team is indeed working on special projects this could mean that Intel will have new surprises waiting in the wings to be added to X86 designs in the next few years. Also, as I've already mentioned, Nehalem may indeed have extra tricks in its design that have been inherited from the aborted Tejas work. An onboard memory controller shouldn't be a problem since Intel has already worked on this for Timna and obviously has been making full blown memory controllers for years in its chipsets.

In addition to the single main design team that AMD has maintained they have had another design team doing chipsets. It was four years from the 750 chipset to the 8000 chipset with the upgraded 760 and 760MP chipsets in between. The importance of chipsets for AMD is difficult to overstate. AMD's K6 processor was fully capable of dual socket operation. However, no chipset existed that would allow K6 to do this. It is also clear that without AMD's 750 chipset that it would have been nearly impossible for AMD to get support for K7's Slot A. It is also clear that without the 760MP chipset that Athlon MP's dual socket capability would have gone for nothing as it did on K6. And, there is no doubt that support for Opteron was nonexistent without the 8000 chipset. I think it is clear though that the effort of designing additional chipsets exceeded AMD's abilities and this ultimately led to the decision to purchase ATI. We know that a lack of a proper chipset prevented dual socket motherboards for K6 and that it was only AMD's in-house 750, 760MP, and 8000 chipsets that allowed proper support for K7, AthlonMP, and Opteron. AMD could have skipped the ATI purchase but we would have to wonder if AMD would be able to keep up with new chipsets to keep future chip capabilities from falling by the wayside. I think a similar argument can be made that Intel's primary motive in switching to an onboard memory controller is the geometrically increasing difficulty of designing the Caneland quad FSB chipset.

Finally, we have to wonder just how well it can work for both AMD and Intel to switch to two year design schedules instead of four. For every design that was newly created in the past there was a period of upgrade. Obviously one team had to be working on the new "clean" design while another smaller team concentrated on the upgrade. There is no doubt that for engineers the relative clean slate of a new design was more exciting and offered fewer limitations. It is also the case that a new architecture will demonstrate the largest improvement. In this regard it can be seen that the upgrade team is the perpetual underdog with far greater restrictions and less improvement. The two year design cycle requires dropping two separate teams and blending the upgrade and new design teams together. This makes the upgrade cycle more rewarding because there will be larger improvements. This does create greater restrictions for the new design team because they both have to work within the existing architecture and because not all ideas can be incorporated in the shorter cycle time. However, no really good idea needs to die because each good idea can potentially be included in the next upgrade or the one after. Apparently Intel has already moved in this direction while AMD has responded by making the CPU core modular. AMD's modular die allows some "black box" modification. In other words, AMD can always assign engineers to trouble areas and these engineers can make the necessary changes to that module without worrying about the rest of the die. This ability to isolate problem areas saves a great deal of iterative design work. There is no indication yet of modular design from Intel but then Intel probably has the manpower to deal with this and may prefer the greater flexibility of a non-modular design.

How we got here is one of the important ways of seeing where we are going. I have confidence in the K10 design because it matches AMD's historic four year design pattern. Likewise Nehalem at five years beyond Prescott matches a similar pattern. Obviously though, until Nehalem appears we won't know if any of the Tejas design work made it into Nehalem, nor do we know much about it other than the Integrated Memory Controller and CSI. However, given Timna and Intel's great experience with chipset memory controllers I can't imagine that the IMC would be a problem. Likewise, Intel's PCI-e initiative in 2006 should generate the necessary hardware to make CSI a reality. I suppose we will have to wait until AMD's K11 to see just how well the new modular approach is working.

My final thought is that the doubling of SSE speed by both C2D and K10 can't be very good news for the Itanium design team. Clock speeds shot upward from K6's 166Mhz to K7's 1000 MHz in just two years while Intel matched pace with Pentium II and then Pentium III. I believe there is no doubt that this more than anything caused Intel to miss its initial performance objectives with Merced Itanium. One has to wonder if a Nehalem with SSE4, IMC, and CSI might be a serious threat to the next generation Itanium. Nor is Itanium alone. Eventually, even IBM's mighty Power will come under siege from powerful but cheaper X86's.