The Eye Of The Storm

At the same time that people on the web are insisting that AMD is spinning its statements to cover up failures with K10, I've seen many of these same people frantically spinning the news in the opposite direction by interpreting any snippet of information in the worst possible way against AMD. If there are indeed cyclonic and anti-cyclonic forces at work then perhaps somewhere in the center we can find something that makes sense.

The only way to reach any conclusions about AMD is to start with what we know. We know that AMD first demonstrated Barcelona November 30, 2006. This was presumably a stable Alpha chip. The earliest Conroe's were also Alpha chips and we know that it took Intel about six months to go through two revisions to get to the B1 release version. However, we also know that Intel's B1 had a minor bug that was fixed in the B2 revision, so B2 is also a reasonable assumption for production. We know too that the fastest that AMD could run off inline test chips would be 10 weeks. So, if we project this from the November 2006 demo we get:

November 30, 2006 – Stable Alpha silicon demo
February 8, 2007 – B0
April 19, 2007 – B1
June 28, 2007 – B2 (originally intended launch?)

Since AMD gave another demonstration in May we can assume that this followed the B1 revision. They could not have been waiting on a B0 revision since, even with delays, this would have been ready no later than March. It is reasonable to assume that they managed to squeeze in a B0 and B1 and then gave a demo shortly after B1 would have been ready. However, the fact that AMD did not give another demo when B0 was ready suggests that B0 was probably not much better than the A1 revision. Notice too that we have good correlation between the B2 revision and AMD's stated time frame of mid year since the B2 revision should have been ready by mid July even with some delay. So, we are probably on the right track. But, what if the B2 chip isn't the actual volume production chip and AMD needs another revision? Projecting further we would get:

September 6, 2007 – B3
September 23, 2007 – Calendar End of Summer.

With two and a half weeks of margin, this suggests that a B3 revision could probably be released before the calendar end of Summer. So, again we have good correlation with AMD's latest statement about release by end of Summer. Typically, you don't commit large amounts of production capacity to a new design until you are sure that the die is production ready. If AMD's B1 revision had been ready then it would have committed for B2 and the launch would be July. However, if B1 still had a nasty bug or two then it would take the B2 revision to fix it and production would not be committed until B3. In other words, AMD could have good production samples at the end of June or early July with B2 but with only testing run volumes probably too few for a genuine launch.

If you launch a product with nothing but ES samples then that is a paper launch. This is pretty much what Intel did when it previewed Conroe six months before availability and what it has repeated with Penryn. If you launch with final version samples but volume won't be up for two or three months then that is a soft launch. To get a genuine launch your volume run must be available within a month. Since it takes two and half months for wafers to run through production this means that you would have to wait about two months after you had a good sample batch to give the volume run time to be ready. If AMD only has a small sample B2 run available in late June or early July then this could be a soft launch unless they wait until late August to launch. There is some small possibility that AMD could gamble and start a small production run early knowing that they might have to scrap it if the samples don't measure up. This is probably the only way that AMD could do a firm launch in July.

We can also reasonably guess that once a production run is started for Barcelona that AMD will begin a Phenom batch about a month later. This probably means a lot more delay than with Barcelona. For example, AMD might be willing to gamble a small production run for server chips since these are low volume anyway but probably would not be willing to gamble with the much larger batch of desktop chips that would be needed. So, even if AMD had enough Barcelona chips for a reasonable launch in July it is still almost a certainty that the desktop chips would be delayed until October. Again, these speculative dates seem to match well with what we've been hearing lately.

I was a bit surprised when some suggested that the lack of an elaborate showing by AMD at Computex meant something. However, if you look at the 2006 Computex, AMD showed almost nothing beyond AM2 systems and motherboards, and AM2 had been officially released a month earlier. The real information was given at AMD's June 2006 Technology Analysts meeting. Since nothing was released right before the 2007 Computex this year, I'm not surprised that it seemed so barren. This year, it looks like AMD is pushing the meeting back one and a half months and “will hold its 2007 Technology Analyst Day on Thursday July 26th, 2007”. The push to a later date probably has to do with the fact that DTX and mini-DTX motherboards are due in August as much as the time frame for K10. July also makes sense because FAB 30 should be into the 300mm conversion and FAB 36 should be working on 45nm, and AMD will surely want to mention them. AMD will probably have some word about the repaired R650 GPU series by then along with a time frame for R700. Most importantly though AMD would know by then if the June B2 batch is ready for production.

Our assumption so far has been that B2 will probably be a good batch with volume coming with the B3 batch. This has led some to speculate that a bad B2 batch would knock K10 out for the rest of the year since presumably they would have to wait until the B3 test run to commit for B4 and this would arrive too late for Q4 sales. However, this scenario is not likely to happen. If B2 turns out bad then AMD will have little choice but to start full production with B3 and gamble that it will be good enough to sell. In other words, if AMD is that late with K10 then they will have to perform without a net knowing that a bad B3 batch will cost them millions in scrapped silicon.

The next issue is performance. Back in January, Randy Allen at AMD stated that K10 would be 40% faster than Intel's best Clovertown. And, presumably this would be with the 2.5Ghz speed K10. At the time that Allen said this, Clovertown was only projected to clock to 2.66Ghz. K10 would have needed a boost of about 25% over K8 to hit this performance level. This was possible but Penryn changes things considerably. So to figure out how it might compare with Penryn we have, 1.4 X 2.66Ghz = 3.724Ghz for Clovertown. However, Intel has stated that Penryn is 9% faster than Clovertown. Therefore, 3.724Ghz / 1.09 = 3.42Ghz for Penryn. Interestingly, this is only 2.5% faster than Intel's expected 3.33Ghz speed for Penryn. Recalling that since 3% is the margin of error in testing, a 2.5% difference is not significant. So, we seem to have correlation between Penryn's expected performance and launch speed and AMD's earlier relative performance estimate. By the look of it, Intel intended that a 3.33Ghz Penryn would match whatever AMD could release. Personally, I think AMD's January estimate was a bit too high and rather than 2.5Ghz it will take a K10 more like 2.8Ghz to match a 3.33Ghz Penryn. 2.8Ghz for quad core K10 is looking less and less likely in 2007 while 3.33Ghz Penryn seems much more likely. Roughly speaking, this could allow Intel to hold onto a 10% lead on all single and dual socket systems.

My estimate is based in part on the architectural changes. Of course, I've also seen lots of people trying to pull some kind of estimate of performance out of the two benchmarks that have been done. The problem is that A1 silicon is usually bogged down by patches and won't really show performance. I can already hear Intel enthusiasts insisting that this can't be true because Intel demoed A1 silicon with Conroe. Well, not exactly. Intel's initial silicon was so slow that they had to overclock it with water cooling. This is why they wouldn't let anyone look inside the case. Secondly, Intel very, very carefully controlled what benchmarks were used. They left out most benchmarks and only used what wasn't affected by the BIOS patches. Then, when B0 was ready and needed fewer patches they loosened up a bit and allowed more benchmarks. They were clearly confident by the time B1 was released so we can be certain that it required no major BIOS patches. We know that B1 still contained a bug but this was apparently not so severe that it hurt the benchmark scores. However, this does not seem to be the case at all with K10. Since AMD did not demo a B0 revision it must have still been heavily patched. And, the very limited demo in May with the B1 revision makes it likely that the chip was still using heavy enough BIOS patches to knock the performance down. Remember though that no vendor or partner has anything newer than B1 since the B2 chips won't be ready until the end of the month.

I have heard some insist though that the B1 revision is “final silicon” and therefore whatever benchmark scores have been seen must indicate true performance. However, this is obviously not the case since if B1 were final then K10 would be launched in volume with B2 and there would be no question of when it would be available. In other words, we can't claim that K10 is delayed because it is buggy and then claim that the silicon is still good enough for valid benchmark scores.

Nevertheless, the negative speculation about AMD's actions is unending so let's see if we can cover each point:

The first possibility is that K10 has a major architectural flaw that is causing the low benchmark scores. We saw this with Intel with both Williamette and Itanium. However, this would not explain a delay since major flaws take at least a year to fix. AMD would have to launch K10 as it is in spite of the low performance just as Intel did with Williamette and Itanium.

The second possibility is that K10 is complete but is running hot like Prescott did. Prescott was delayed for months until the BTX standard fixed both the cooling problems and the high socket power draw. This argument doesn't work though because Prescott was actually released right away as the lower clocked Celeron D. Likewise, Intel released Smithfield at lower clocks when heat and power draw were a problem. AMD would simply follow suit and release lower clock speeds of K10 which would easily replace 3800+ and at least compete with with C2D 6300 and below. AMD would probably also release a quad FX version since these platforms could handle more heat and power draw. With its enhanced SSE performance there is no doubt that even a lower clocked K10 would add value to the current offerings. There is also no doubt that AMD desperately needs a quad core offering in whatever form it can produce. Even at low clock speeds a quad core would still be launched just as Smithfield was for dual core.

A similar argument is that K10 is in finished form (and therefore the scores are valid) but that AMD is having process and yield problems and this is why the chip is delayed. However, we've already seen that if speeds were a problem that AMD would release anyway. Also, when K8 was first released in 2003, the yields were not only bad but were the worst that AMD has ever had. Yet, that didn't stop them from launching with 1.4 - 1.8Ghz chips that were no faster than the 2.2Ghz Barton. And, with the large drops in volume in Q1 AMD would have enough idled capacity even if the yields are poor. So, if yields or speeds were a problem then K10 would be launched at low speeds and then bumped up as AMD was able. Finally, even with low yields, AMD could produce enough K10's to cover the server segment where volumes are low and margins are much better than on the desktop as they did with K8.

The most logical assumption remains that the delay is caused by bugs in the die that require BIOS patches to run. This then degrades the performance and causes the low benchmark scores. A patch that did not degrade performance would not cause a delay. A serious design flaw would likewise not cause a delay. Process or yield problems would only cause the initial clock speeds to be lower rather than causing a launch delay.

I've seen commentors on my blog and web authors (who should know better) claim that silence by AMD on these matters will erode confidence and hurt AMD's sales. These people tend to forget that the tiny percentage (less than 0.1%) of enthusiasts who really care about top performance are only a tiny fraction of sales. Also, this crowd tends to be very fickle and will quickly swap systems if any advantage becomes apparent. There are people who read information on the internet who aren't looking for the highest possible performance but this group tends to have brand loyalties anyway. The fact is that probably 95% of all people who may buy a computer in the next year have never heard of Barcelona or Agena and will not notice or care if it is delayed. The only people who really matter are the ones who make purchasing decisions for Dell, HP, and Gateway since the chips have to actually be in systems before they will be purchased by most consumers. And, not surprisingly, buyers for major vendors get their information from private demonstrations rather than reading reviews on the internet. AMD is not likely to give out much information before the 2007 Technology Analyst Day and this is probably when they will announce firm release dates for K10. If some find this fact frustrating then perhaps they should consider the lyrics to the Go Go's song, Our Lips Are Sealed.