Q3 2007 Earnings, AMD & Intel

With AMD's Q3 Earnings information added to Intel's we can see that Intel is doing quite well while AMD is still struggling. Nevertheless the announcements have dispelled many rumors that have followed the two over the course of this year.

Intel's revenues and margins are up this quarter and it is obviously doing well. In contrast AMD lost $400 Million and has much lower margins. One could be forgiven for confusing today with early 2003 when Intel was doing well and AMD was struggling to turn a profit as K8 was released. However, today is quite different from 2003 since AMD is now firmly established in servers, mobile, and graphics. In early 2003 AMD had barely touched the server market with Athlon MP, had only a single chipset for Opteron and had yet to create mobile Turion. It is interesting though to review the common rumors that have surrounded Intel and AMD this year to see where perception differs from reality.

A commonly repeated rumor was that AMD was teetering on the edge of bankruptcy and would likely have to file after another bad quarter or two. However, it is clear from the reduction in stock holder equity this quarter that AMD could survive at least another year with similar losses each quarter. If AMD improves in Q4 then bankruptcy seems unlikely. Also along these lines was the persistent rumor that AMD would sell FAB 30. AMD's announcement of pilot conversion to 300mm/45nm (as I indicated months ago) shows that AMD will not be forced back to a single FAB.

A similar myth was that AMD would need to be purchased by another company to be bailed out. The biggest problem with this idea is that there really isn't anyone to buy AMD. Companies like Samsung and IBM would be competing with their own customers with such a purchase and companies like Texas Instruments and Motorola have been out of the frontline microprocessor business for many years.

It has often been suggested that Intel could simply flood the market with bargain priced chips to deprive AMD of revenue. However it is clear from Intel's statements that they were unable to meet demand during the third quarter without drawing down inventories. Since the fourth quarter is typically the highest volume of the year it is unlikely that Intel will be able to cover all of the demand. Leaving Q4 with lower inventories would further prevent Intel from capturing additional demand in Q1. This means that Intel will likely be unable to really squeeze AMD until the second quarter of 2008 when 45nm production is up to speed and demand falls off from Q1 08.

Lately, it has been fashionable to suggest that AMD was abandoning the channel yet AMD posted record sales to the channel in Q3. It was also common to see bashing of ATI's offerings versus nVidia. Yet the increased sales from chipsets and graphics indicate that ATI is gaining ground after its loss of direct business with Intel. The ATI assets should continue to add to profits in Q4. Secondly, as AMD and nVidia strive to gain advantage there is no doubt that Intel is being left behind. With new chipset offerings from AMD in Q4 and Q1, Intel's chipsets will once again be second rate in terms of graphics. The company most likely to be hurt is VIA as the move by Intel and AMD into the small form factor mini-ITX size commoditizes the market and removes most of the previous profits. One has to wonder how much longer VIA can stay in this market as it gets squeezed both in terms of chipsets and low end cpu's. One has to wonder as well if Transmeta might soon become an AMD acquisition as it similarly struggles at the low end.

Intel was often described as moving its 45nm timetable forward one quarter while AMD was often described as falling further and further behind. However, the demand shortages would be consistent with rumors that Intel was having trouble moving 45nm production beyond D1D before Q1 08. Presumably the Penryn chips that will be available in Q4 07 will be from D1D. AMD's statement countered rumors of a slipping 45nm schedule by repeating its timetable of first half of 2008. Intel's supposed one quarter pull in for 45nm was clearly ficticious since Intel's own Tick Tock schedule would be Q4 2007 or exactly two years since 65nm in Q4 2005. So, Intel is on schedule rather than moving the schedule forward. AMD's statement was a bit of a surprise since the previous timeline had been "midyear" for 45nm. This could easily have been Q3 but AMD's wording of first half of 2008 means late Q2 is more likely. If AMD really is on this track then half of Intel's previous process lead will be gone in another two quarters. This would also mean that AMD will have moved to 45nm in just 18 months rather than 24 months as Intel has done.

A current area of confusion is whether demoed chips are at all representative of actual production. It has become apparent that Intel's initial production from D1D is of very high quality. However, quality seems to fall somewhat as production is moved to additional FABs. In the overclocking community, it has been suggested that Intel's bulk production did not catch up to the quality of the early D1D chips until the recent release of the G0 stepping. This suggests that Intel's bulk production quality lags its initial production quality by a full year. This would seem to explain both having to destroy the initial 45nm chips. Clearly, Intel's demos are not indicative of actual production as seen by the lack of chips clocked above 3.0Ghz. This leaves the question of whether AMD's demo of a 3.0Ghz K10 was similarly cherry picked. A late Q1 or early Q2 08 release of a 3.0Ghz FX Phenom would be consistent however a late Q2 release would mean that AMD was equally guilty.

A lot of faith was put into Intel's mobile Centrino position. However, this quarter it is clear that Intel lost some mobile ground. Intel faces a much greater challenge as Griffin is released with an all new mobile chipset in Q1 08. All early indications are that mobile Penryn is unable to match Griffin's power draw. This will likely mean continued erosion of Intel's mobile position.

The server market is another area that tends to run counter to rumors. After Intel's very strong showing with Woodcrest and Clovertown it has taken about as much 2-way share from AMD as it can. The suggestion has been that Intel could hold its 2-way share while taking 4-way share from AMD with Tigerton. This scenario is almost certainly incorrect. Barcelona should provide strong competition in 2-way servers from Q4 07 forward so Intel is likely to lose some of its server share. And, Tigerton is only a slightly modified 65nm Clovertown which will have great difficulty overcoming the high power draw of its quad FSB, FBDIMM chipset. This makes it unlikely for Tigerton to do more than hold the line as a replacement for Tulsa. It appears that Intel's true 4-way champion, Nehalem, won't arrive until Q4 (the normal Tick Tock schedule) by which time AMD's 45nm Shanghai will already be out. I have no doubt that Nehalem could show very well against Shanghai since Nehalem will have more memory bandwidth. However, a big question is whether this will move down to the desktop. There still seems to be some confusion too as to whether or not Intel is really willing to discard its lucrative chipset sales and FSB licensing. The strength of Nehalem is also a two edged sword as Intel will simultaneously lose its die size (and cost) advantages since Nehalem is a true monolithic quad core die. Power draw is also unclear until it is known whether Nehalem has a direct IMC or some type of intermediate bus like AMD's G3MX. For example if Nehalem relies on FBDIMM as the current C2D generation does then Nehalem may have a tough time being competitive in performance/watt.

It now appears that AMD has indeed moved up its own timetable for delivering 2.6Ghz chips. These seem scheduled for release in Q4 whereas the previous roadmap had them appearing in Q2 08. This would likely mean 2.8Ghz chips in Q1 from AMD however Intel could maintain a comfortable lead with 3.1Ghz or faster chips of its own. The number of partners added to IBM/AMD research consortium also vanquished persistent rumors that AMD would toss SOI on 32nm.

However, the most surprising thing that has come up is AMD's view of the market. The popular wisdom was that AMD would be forced to back down and give up share to Intel. Yet in spite of Intel's good showing in profits, AMD is determined to increase revenues to $2 Billion a quarter. This would mean not only holding onto current share but taking more share from Intel. The $2 Billion mark is unlikely soon but it does seem that a near term loss of, say, $100-200 Million would be considerably better than the current $400 Million loss. The $2 Billion goal also seems to fit with AMD's previously stated goal of 30% share by end of 2008. I don't have AMD's volume share numbers yet for Q3 but I recall 23% from Q2. If AMD is at, say, 24% now then a 25% increase would be 30% and a similar 25% increase with the $1.6 Billion gross revenue would be $2 Billion. Assuming that AMD can hit its 45nm Shanghai target, I can't see any reason why this wouldn't be possible. It would mean ramping FAB 36 by the normal schedule and then partially ramping FAB 38 in Q1 and Q2. This would allow production to increase in Q2 and Q3 which would keep delivered chip volume increasing in Q3 and Q4 when FAB36 will already be topped out. Since Intel's 45nm ramp is slower than AMD's it is possible for AMD to blunt Intel's price advantage as long as Shanghai stays on track.

In spite of the rumors that have been dispelled we are left with a number of unanswered questions. Is there a bug that is holding back K10's performance? What speeds will Intel and AMD have in Q1? Is Intel really willing to toss its chipset revenue with Nehalem while losing its current cost advantages? Will the additional partners that have joined IBM and AMD in SOI research allow AMD to match or even exceed Intel's process tech? Can AMD really increase its share by 25%? Is AMD's faster adoption of Immersion a technical advantage or a technical curse? Will Shanghai be able to catch Penryn or hold AMD's position against Nehalem? The sad part is that it will take another year to know all of the answers for certain.

Waiting For The Wind To Blow

We seem to be trapped in the Doldrums lately, waiting. We wait for faster clocks and desktop versions of K10 from AMD and 45nm desktop chips from Intel. We wait to find out just how things really stack up.

I'm familiar with the changes in architecture between K8 and K10. These changes are quite good but, strangely, we haven't seen this reflected in the Barcelona reviews. We are well past the point of pretending that everything is normal at AMD. It seems to me that there are only four possibilities:

1. The benchmarks are not complied properly for K10.
   
   
2. The reviews were not very high quality.
   
   
3. There is a bug in the revisions that have been tested.
   
   
4. There is a major flaw in the K10 architecture.

It wouldn't surprise me if a lot of the standard benchmarks we see claiming to compare Clovertown with Barcelona actually use the Intel compiler which has been known for quite some time to handicap AMD processors. There has also been some suggestion that Intel has spent time tuning their code specifically for these benchmarks.

There is also little doubt that the Barcelona reviews were both rushed and sloppy, much sloppier the usual testing we see from places like Anandtech. However, even the Tech Report review was disappointing since the author didn't seem to have much grasp of the technical aspects of K10.

However, I've also seen benchmarks at SPEC. These are somewhat difficult to compare because the IBM sponsored scores change both operating system and compiler when moving from K8 Opteron to K10 Opteron. Taken at face value these would show an increase in core speed of 11% for FP and 14% for Integer for K10. A 14% increase in Integer is good enough that I can't say categorically that it is incorrect. However, the FP score is a problem since the FP pipeline for K10 should be nearly 100% faster. It's hard to claim that it wasn't compiled correctly because it used Portland Group's compiler which should fully support K10. In fact, AMD has been working closely with Portland Group to ensure that it does. We also can't claim test bias because the testing was performed by AMD itself.

Given the SPEC scores created by AMD with the PGI compiler, I think we have to assume that K10 either has a bug that hasn't been fixed yet or has a serious architectural flaw that is preventing full FP speed. Earlier I had wondered if K10 had a bug in the L1 cache. This still seems to be a strong possibility. The problem is that this type of bug would not appear in the list of errata. Secondly, as strapped for cash as AMD is these days they would have no reason to make this public since it would likely mean fewer K10 sales. The only real difference between a bug and a major flaw is how long it takes to fix it. In terms of architecture, something like an L1 cache bug should be fixable in six months.

A minor bug could be fixed in as little as eight weeks (if rushed) but it would take another month for the new chips to get into circulation. However, for a standard run the fix would take fifteen weeks and at least another month to ship. So, four and a half to six months would be typical. The problem however is that the 45nm version, Shanghai, runs with the same circuitry so a flaw in K10 pushes Shanghai back until the flaw is fixed. The fact that no tapeout announcement for Shanghai has been made yet supports this scenario. AMD originally planned to release Shanghai at midyear so tapeout should have occurred in July. AMD has maintained that the 45nm immersion process is on track so this would seem to only leave a design problem. If this is indeed the case then this is both good and bad. It is clearly bad because the last thing AMD needs at this point is another problem getting in the way of competitive production. However, in an odd way I suppose it would be good if the test scores we've seen do not represent the actual potential of K10. For now there is nothing to do but wait.

The Top Developments Of 2007

It looks like both AMD and Intel have been as forthcoming as they are likely to be for awhile about their long range plans. The most significant items however have little to do with clock speeds or process size.

The two most significant developments have without doubt been SSE5 and motherboard buffered DIMM access. AMD has already announced its plan to handle motherboard buffered DIMMs with G3MX. This is significant because it means the end of registered DIMMS for AMD. With G3MX, AMD can use the fastest available desktop DIMMs with its server products. This is great for AMD and server vendors because desktop DIMMs tend to be both faster and cheaper than register DIMMs. This is also good news for DIMM makers because it would relieve them making registered DIMMs for a small market segment and allow them to concentrate on the desktop products. Intel may have the same thing in mind for Nehalem. There have been hints by Intel but nothing firm. I suppose Intel has reason to keep this secret since this would also mean the end of FBIMM in Intel's longterm plans. If Intel is too open about this it could make customers think twice about buying Intel's current server products which all use FBDIMM. So, whether this is the case with Nehalem or perhaps not until later it is clear that both FBDIMM and registered DIMMs are on their way out. This will be a fundamental boost to servers since their average DIMM speed will increase. However, this could also be a boost to desktops since adding the server volume to desktop DIMMs should make them cheaper to develop. This also avoids splitting the engineering resources at memory manufacturers so we could see better desktop memory as well.

SSE5 is also remarkable. Some have been comparing this with SSE4 but this is a mistake. SSE4 is just another SSE upgrade like SSE2 and SSE3. However, SSE5 is an actual extension to the x86 ISA. If AMD had been thinking clearer they might have called it AMD64-2. A good indication of how serious AMD is about SSE5 is that they will drop 3DNow support in Bulldozer. This clears away some bit codes that can be used for other things (like perhaps matching SSE4). Intel has already stated that they would not support it. On the other hand, Intel's statement means very little. We know that Intel executives openly lied about their intentions to support AMD64 right up until they did. And, Intel has every reason to lie about SSE5. The 3-way instructions can easily steal Itanium's thunder and Intel is still hoping (and praying) that Itanium will not get gobbled up by x86. Intel is also stuck in terms of competitiveness because it is too late to add SSE5 to Nehalem. This means that Intel would have to try to include it in the 32nm shrink which is difficult without making core changes. This could easily mean that Intel is behind in SSE5 until 2010. So, it wouldn't help Intel to announce support until it has to since supporting SSE5 now would only encourage development for an ISA extension that it will be behind in. Intel is taking the somewhat deceptive approach of working on a solution quietly while claiming not to be. Intel can hope that SSE5 won't become popular enough that it has to support it. However, if it does then Intel can always claim to be giving in to popular demand. It's dishonest but it is understandable for a company that has been painted into a corner.

AMD understands about being painted into a corner. Intel has had the advantage with MCM quad cores since separate dies mean both higher yields and higher clock speeds. For example, on a monolithic quad die you can only bin as high as the slowest core. However, Intel can pick and choose individual dies to put the highest binning ones together. Also, Intel can always pawn off a dual core die with a bad core as a lowly Conroe-L but it would be a much bigger loss for AMD to sell a quad die as a dual core. AMD's creative solution was the Triple Core announcement. This means that any quads with a bad core will be sold as X3's instead of X4's. This does make AMD's ASP look a bit better. I doubt Intel will follow suit on this but then it doesn't have to. For AMD, having an X4 knocked down to an X2 is a big loss but for Intel it just means having a Conroe knocked down to Conroe-L which is not so big. Simply put, AMD needs triple cores but Intel doesn't. On the other hand, just as AMD was forced to release a faster FX chip on the older 90nm process so too it seems Intel has been forced to deliver Tigerton not with the shiny new Penryn core but with the older Clovetown core. Tigerton is basically just Clovertown on a quad FSB chipset. This does suggest at least a bit of desperation since after working on this chipset for over a year Intel will be lucky if it breaks even on sales. To understand what a stumble Tigerton is you only have to consider the tortured upgrade path. In 2006 and most of 2007 Intel's 4-way platform meant Tulsa. Now we get Tigerton which uses the completely incompatible Caneland chipset. No upgrades from Tulsa. And, for anyone who buys a Tigerton system, oops, no upgrade to Nehalem either. In constrast, 4-way Opteron systems should be upgradable to 4-way Barcelona with just a BIOS update. And, if attractive, these should be upgradable to Shanghai as well. After Nehalem though, things become more even as AMD introduces Bulldozer on an incompatible platform. 2009 will without doubt be the year of new sockets.

For the first time in quite awhile we see Intel hitting its limits. Intel's 3.33Ghz demo had created the expectation of cool running 3.33Ghz desktop chips with 1600Mhz FSBs. It now appears that Intel will only release a single 45nm desktop chip in 2007 and it will only be clocked at 3.0Ghz. The chip only has a 1333Mhz FSB and draws a whopping 130 Watts. Thus we clearly see Intel's straining to deliver something faster much as AMD did recently with its 3.2Ghz FX. However, Intel is not straining because of AMD's 3.2Ghz FX chip (which clearly is no competition). Intel is straining because of AMD's server volume share. In the past year, AMD's sever volume has dropped from about 25% to only 13%. Now with Barcelona, AMD stands to start taking share back. There really isn't much Intel can do to prevent this now that Barcelona is finally out. But any sever chip share that is lost is a double blow because server chips are worth about three times as much as desktop chips. This means that any losses will hurt Intel's ASP and boost AMD's by much more than a similar change in desktop volume would. So, Intel is taking its best and brightest 45nm Penryn chips and allocating them all to the server market to try to hold the line against Barcelona. Of the 12% that Intel has gained it is almost certain to lose half back to AMD in the next quarter or two, but if it digs in, then it might hold onto the other half. This means that the desktop gets the short end of the stick in Q1 2008. However, by Q2 2008, Intel should be producing enough 45m chips to pay attention to the desktop again. I have to admit that this is worse than I was expecting since I assumed Intel could do a 3.33Ghz desktop chip by Q1. But now it looks like 3.33Ghz will have to wait until Q2.

AMD is still a bit of a wild card. It doesn't appear that they will have anything faster than 2.5Ghz in Q4 but 3.0Ghz might be doable by Q1. Certainly, AMD's demo would suggest a 3.0Ghz in Q1 but as we've just seen, demos are not always a good indicator. Intel's announcement that Nehalem has taped out is also a reminder that AMD has made no such announcement for Shanghai. AMD originally claimed mid 2008 for Shanghai and since chips normally appear about 12 months after tapeout we really should be seeing a tapeout announcement very soon if AMD is going to release by Q3 2008. There is little doubt that AMD needs 45nm as soon as possible to match Intel's costs as Penryn ramps up. A delay would seem odd since Shanghai seems to have fewer architecture changes than Penryn. AMD needs a tapeout announcement soon to avoid rumors of problems with its immersion scanning process.