tag:blogger.com,1999:blog-32351755.post8788980806301326894..comments2023-08-01T11:15:10.503-04:00Comments on Scientia's Blog: Updates And Old PatternsScientia from AMDZonehttp://www.blogger.com/profile/11307174874527564058noreply@blogger.comBlogger36125tag:blogger.com,1999:blog-32351755.post-26566873115101544902008-04-26T12:35:00.000-04:002008-04-26T12:35:00.000-04:00popI'm not as familiar with the nVidia products as...<B>pop</B><BR/><BR/>I'm not as familiar with the nVidia products as the ATI. I know with ATI they suggest overlapping some types of manipulations with the moves to local memory to increase the effective throughput. By doing this you can cut the processing time in half.<BR/><BR/>Again, I don't know about the nVidia products but ATI has DMA so it can access memory on its own. However, this would beScientia from AMDZonehttps://www.blogger.com/profile/11307174874527564058noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-62919580675690479622008-04-24T11:09:00.000-04:002008-04-24T11:09:00.000-04:00"Ho Ho said... What is the difference between G..."Ho Ho said...<BR/><BR/> What is the difference between GPU pulling textures, vertices and shaders into its caches/local memory and CPU pulling the same stuff to its caches? "<BR/><BR/>There's a big difference. <BR/>As nVidia said regarding CUDA, GPUs aren't optimized for memory access but for ALU operations. On video processors there are no implicit memory access caches (yes there are no Pop Catalin Severhttps://www.blogger.com/profile/10767225265147312372noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-46736474612240574902008-04-23T02:19:00.000-04:002008-04-23T02:19:00.000-04:00What is the difference between GPU pulling texture...What is the difference between GPU pulling textures, vertices and shaders into its caches/local memory and CPU pulling the same stuff to its caches? <BR/><BR/>Or was your point about the "external memory" that CPU has to feed all the data over PCIe to GPU memory? If so then this is not the only big bottleneck in GPGPU. What I and spam were talking about was the latency there is when all the Ho Hohttps://www.blogger.com/profile/00177815588184912351noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-63962140269194255362008-04-22T14:20:00.000-04:002008-04-22T14:20:00.000-04:00ho ho"Wrong. GPUs have had caches for ages. Where ...<B>ho ho</B><BR/><BR/><I>"Wrong. GPUs have had caches for ages. Where do you get your information, anyway?"</I><BR/><BR/>Let me see if I get this straight. You fancy that telling me that GPU's have local memory is new information? Remarkable that you could be so confused. I was referring to getting information into the GPU, not execution from local memory.Scientia from AMDZonehttps://www.blogger.com/profile/11307174874527564058noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-90922649091519958762008-04-22T02:40:00.000-04:002008-04-22T02:40:00.000-04:00scientia"Most of the latency for GPU operations co...<B>scientia</B><BR/><I>"Most of the latency for GPU operations comes from having to transfer to and from its memory since it is treated as an external device."</I><BR/><BR/>Wrong. GPUs have had caches for ages. Where do you get your information, anyway?Ho Hohttps://www.blogger.com/profile/00177815588184912351noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-22374516353216823662008-04-20T12:01:00.000-04:002008-04-20T12:01:00.000-04:00Most of the latency for GPU operations comes from ...Most of the latency for GPU operations comes from having to transfer to and from its memory since it is treated as an external device. When executed properly GPU operations can still be 5-20X faster. GPU operations make sense when you are dealing with data blocks of sufficient size.Scientia from AMDZonehttps://www.blogger.com/profile/11307174874527564058noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-53805157896011919312008-04-19T07:50:00.000-04:002008-04-19T07:50:00.000-04:00Well, I was rushed and said a few things a bit off...Well, I was rushed and said a few things a bit off in the above post. Still, the latency issue is extreme...Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-32351755.post-65801190893916055702008-04-18T21:31:00.000-04:002008-04-18T21:31:00.000-04:00Look, here's the thing:SSE/X87 have a fairly short...Look, here's the thing:<BR/><BR/>SSE/X87 have a fairly short latency and a fairly low bandwidth. Say, roughly around 4 cycles for a complex SSE op. However, the GPU has latency in the hundreds of cycles. At first glance, this sounds ridiculous. Under closer examination, one realizes that the GPU can do one DP FP op per cycle, MUL/DIV/etc regaurdless. <BR/><BR/>GPU's are insane for these tasksAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-32351755.post-900060694672441462008-04-18T16:25:00.000-04:002008-04-18T16:25:00.000-04:00enumaeI have no idea from that description. It sou...<B>enumae</B><BR/><BR/>I have no idea from that description. It sounds similar to what was said before but nothing specific. By that statement he could mean release in Q3 with volume in Q4 or release and volume in Q4. It could also mean either early Q4 or late Q4. It's still too vague.Scientia from AMDZonehttps://www.blogger.com/profile/11307174874527564058noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-13409766018749325322008-04-18T16:22:00.000-04:002008-04-18T16:22:00.000-04:00ho hoI've tried explaining this to you but you sti...<B>ho ho</B><BR/><BR/>I've tried explaining this to you but you still don't seem to understand. Putting a GPU in the same package connected by HT is no big deal. Just putting a GPU on the same die is functionally equivalent. Both of these would have to be accessed the same as is currently done. No change.<BR/><BR/>However, if the GPU were connected to the actual CPU pipeline then it seems Scientia from AMDZonehttps://www.blogger.com/profile/11307174874527564058noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-59532904052179463002008-04-18T12:12:00.000-04:002008-04-18T12:12:00.000-04:00Patrick Wang - Wedbush Morgan SecuritiesOkay, grea...<I>Patrick Wang - Wedbush Morgan Securities<BR/><BR/>Okay, great, thanks. And then just one last question, just on 45-nanometer, I know that you said that you expect production of that material some time in the summer. Any more color you can provide there, just to help us better understand what’s happening?<BR/><BR/>Derrick R. Meyer<BR/><BR/>We’ll start the production ramp in the summertime and enumaehttps://www.blogger.com/profile/03279137923346047097noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-20097620171100416232008-04-18T04:12:00.000-04:002008-04-18T04:12:00.000-04:00To add to the "gpu instcutions in CPU", you are ba...To add to the "gpu instcutions in CPU", you are basically describing what SSE5/AVX will be. I wouldn't call either of those as "adding GPU instructions to CPU". Only when CPU gets texture sampling instructions/HW I might call it a hybrid GPU. Just adding a bunch of SIMD instructions won't do it. If they would then Power-CPUs have actually been GPUs for years.Ho Hohttps://www.blogger.com/profile/00177815588184912351noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-7896415706145920522008-04-18T04:09:00.000-04:002008-04-18T04:09:00.000-04:00scientia"The big question is whether you could hav...<B>scientia</B><BR/><I>"The big question is whether you could have a GPU act on current MMX or SSE instructions sharing the MMX and XMM registers or whether you would have to have new instuctions"</I><BR/><BR/>In order for this to work efficiently those GPU instructions <I>must</I> be implemented inside the CPU itself. Even a GPU core added to the package will not be efficient enough for majorityHo Hohttps://www.blogger.com/profile/00177815588184912351noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-68249265047782727142008-04-18T02:40:00.000-04:002008-04-18T02:40:00.000-04:00Good news folks:Seems that AMD is planning a Dodec...Good news folks:<BR/><BR/>Seems that AMD is planning a Dodeca core processor, and it seems that it will be some variation of Shanghai.<BR/><BR/><I>AMD engineers reveal details about the company's upcoming 45nm processor roadmap, including plans for 12-core processors<BR/><BR/>"Shanghai! Shanghai!" the reporters cry during the AMD's financial analyst day today. Despite the fact that the company Unknownhttps://www.blogger.com/profile/06169485147097583599noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-5014177941888187482008-04-17T16:45:00.000-04:002008-04-17T16:45:00.000-04:00Ho HoRight now, the GPU is accessed as a completel...<B>Ho Ho</B><BR/><BR/>Right now, the GPU is accessed as a completely separate, external device using library code. You have to specifically transfer data and instructions to the GPU's memory to do any computations.<BR/><BR/>The big question is whether you could have a GPU act on current MMX or SSE instructions sharing the MMX and XMM registers or whether you would have to have new instuctions. AsScientia from AMDZonehttps://www.blogger.com/profile/11307174874527564058noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-62279069135483446872008-04-17T08:10:00.000-04:002008-04-17T08:10:00.000-04:00A verry interesting article :Analysis: AMD Asset L...A verry interesting article :<BR/><BR/><A HREF="http://www.tgdaily.com/content/view/36980/118/1/0/" REL="nofollow">Analysis: AMD Asset Lite strategy will create MAD AMD</A><BR/><BR/>I'll post only the conclusion:<BR/><BR/>"AMD is not going down any time soon and even after the AMD + ATI vs. MAD AMD LLC split, cooperation with IBM, TSMC, Chartered, ANGSTREM will not stop. In fact, it will expand Pop Catalin Severhttps://www.blogger.com/profile/10767225265147312372noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-87966815060412586962008-04-17T03:52:00.000-04:002008-04-17T03:52:00.000-04:00scientia"I didn't say it was a big improvement; ju...<B>scientia</B><BR/><I>"I didn't say it was a big improvement; just that it isn't worse than 90nm as has been claimed."</I><BR/><BR/>I'd say if you get to a lower tech node and do not increase clocks at same thermals on a die-shrink design then things aren't looking well.<BR/><BR/><BR/><I>"A quad processor should therefore need 4X DDR-400"</I><BR/><BR/>For what tasks it would need that much? Any Ho Hohttps://www.blogger.com/profile/00177815588184912351noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-80239986266990375842008-04-16T17:18:00.000-04:002008-04-16T17:18:00.000-04:00Ho Ho said"Are you saying that even though their 6...<B>Ho Ho said</B><BR/><I>"Are you saying that even though their 65nm can get 100MHz more on 65nm they will still top out at same speed at 125W? That isn't all that much improvement I'd say."</I><BR/><BR/>I didn't say it was a big improvement; just that it isn't worse than 90nm as has been claimed.<BR/><BR/><I>"Ah, I see, I thought you were saying that B3 magically got higher IPC than B2."</I><BR/Scientia from AMDZonehttps://www.blogger.com/profile/11307174874527564058noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-3212956604858891682008-04-16T03:08:00.000-04:002008-04-16T03:08:00.000-04:00scientia"It is clear from the TDP that neither the...<B>scientia</B><BR/><I>"It is clear from the TDP that neither the 90nm nor 65nm process could go above 3.2Ghz without exceeding 130 watts."</I><BR/><BR/>Are you saying that even though their 65nm can get 100MHz more on 65nm they will still top out at same speed at 125W? That isn't all that much improvement I'd say.<BR/><BR/><BR/><I>"Actually, 2.4 and 2.5Ghz are faster than 2.3Ghz, patched or Ho Hohttps://www.blogger.com/profile/00177815588184912351noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-53227150480672333322008-04-15T19:37:00.000-04:002008-04-15T19:37:00.000-04:00OK Scientia, it looks like you CAN fit 6 DIMMs on ...OK Scientia, it looks like you CAN fit 6 DIMMs on an ATX MB-it'll be a tight fit though and I'd like to see someone try it. I have no idea how big the G3MX chips are so there may not be enough room to fit those as well. I should caution that some MB manufacturers call a 305mm x 224mm MB an ATX and I am using the Standard ATX definition of 305mm x 244mm. Better to use EATX though-305mm x 330mm.Polonium210https://www.blogger.com/profile/03179220006087088532noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-25667641453761752742008-04-15T15:14:00.000-04:002008-04-15T15:14:00.000-04:00AVX over the existing 128 bit pathways wouldn't ga...AVX over the existing 128 bit pathways wouldn't gain much speed. Also, in K8 the 128 instructions were issued as two 64 bit micro-ops which meant that it took the same amount of decoding time as two 64 bit instructions would have.<BR/><BR/>It could be easier for AMD to do 256 bit operations on the GPU. However, the GPU would have to be beefed up some and AMD would have to think of some way to Scientia from AMDZonehttps://www.blogger.com/profile/11307174874527564058noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-19218065658430321932008-04-15T15:01:00.000-04:002008-04-15T15:01:00.000-04:00Ho Ho"Ok, but what if AMD chose not to release fas...<B> Ho Ho</B><BR/><BR/><I>"Ok, but what if AMD chose not to release faser 65W 90nm CPUs?"</I><BR/><BR/>It is clear from the TDP that neither the 90nm nor 65nm process could go above 3.2Ghz without exceeding 130 watts.<BR/><BR/><I>"They are only faster if you compare against patched system."</I><BR/><BR/>Actually, 2.4 and 2.5Ghz are faster than 2.3Ghz, patched or otherwise.<BR/><BR/><I>"So you areScientia from AMDZonehttps://www.blogger.com/profile/11307174874527564058noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-20407431596654575532008-04-15T10:03:00.000-04:002008-04-15T10:03:00.000-04:00Even with two-pass SIMD it might be faster thanks ...Even with two-pass SIMD it might be faster thanks to less instructions needed to be loaded-decoded.Ho Hohttps://www.blogger.com/profile/00177815588184912351noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-31859297485059559122008-04-15T08:34:00.000-04:002008-04-15T08:34:00.000-04:00256 bit wide instruction don't necesarily mean hig...256 bit wide instruction don't necesarily mean higher performance (2x or close), it all depends on the hardware pipeline width. Intel might implement 256 bit wide sse (AVX) over 128 bit wide hardware pipeline, just like SSE that was implemented over 64 bit wide pipeline prior to Core 2, Barcelona, using instruction breakup.<BR/><BR/>Also AMD could easily provide an AVX compatible instruction set Pop Catalin Severhttps://www.blogger.com/profile/10767225265147312372noreply@blogger.comtag:blogger.com,1999:blog-32351755.post-15732649763040770362008-04-15T03:42:00.000-04:002008-04-15T03:42:00.000-04:00erlindo"1)What probabilities does Shanghai have to...<B>erlindo</B><BR/><I>"1)What probabilities does Shanghai have to include SSE5 instructions?"</I><BR/><BR/>Zero<BR/><BR/><BR/><I>"2) About AVX, why didn't AMD thought of SSE5 to be 256 bit wide instead of being 128 bit?"</I><BR/><BR/>It is a bit easier to work with 128bit than with 256bit (2x2 vs 2x4 quads). Of course if you are smart, plan ahead and can make your algorithms work nicely for Ho Hohttps://www.blogger.com/profile/00177815588184912351noreply@blogger.com